Lines Matching refs:STM32F4_RCC_APB1ENR
32 #define STM32F4_RCC_APB1ENR 0x40 macro
77 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
78 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
79 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
80 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
81 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
82 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
83 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
84 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
85 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
86 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
87 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
88 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
89 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
90 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
91 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
92 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
93 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
94 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
95 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
96 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
97 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
98 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
99 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
100 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
101 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },