442 	u16 clk_val;  member
502 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_unprepare()
517 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_enable()
520 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);  in syscon_clk_enable()
531 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_disable()
534 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_disable()
537 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);  in syscon_clk_disable()
571 	switch(sclk->clk_val) {  in syscon_clk_recalc_rate()
638 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_round_rate()
657 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_set_rate()
698 		    u16 clk_val)  in syscon_clk_register()  argument
723 	sclk->clk_val = clk_val;  in syscon_clk_register()
747 	u16 clk_val;  member
755 		.clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
761 		.clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
767 		.clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
773 		.clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
779 		.clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
785 		.clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
791 		.clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
798 		.clk_val = 0xFFFFU,
804 		.clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
810 		.clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
816 		.clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
822 		.clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
828 		.clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
834 		.clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
840 		.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
846 		.clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
853 		.clk_val = 0xFFFFU,
859 		.clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
865 		.clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
919 						  u3clk->clk_val);  in of_u300_syscon_clk_init()