419 static void __iomem *syscon_vbase;  variable
520 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);  in syscon_clk_enable()
537 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);  in syscon_clk_disable()
559 	val = readw(syscon_vbase + U300_SYSCON_CCR);  in syscon_get_perf()
675 	val |= readw(syscon_vbase + U300_SYSCON_CCR) &  in syscon_clk_set_rate()
677 	writew(val, syscon_vbase + U300_SYSCON_CCR);  in syscon_clk_set_rate()
894 		res_reg = syscon_vbase + U300_SYSCON_RSR;  in of_u300_syscon_clk_init()
895 		en_reg = syscon_vbase + U300_SYSCON_CESR;  in of_u300_syscon_clk_init()
898 		res_reg = syscon_vbase + U300_SYSCON_RFR;  in of_u300_syscon_clk_init()
899 		en_reg = syscon_vbase + U300_SYSCON_CEFR;  in of_u300_syscon_clk_init()
902 		res_reg = syscon_vbase + U300_SYSCON_RRR;  in of_u300_syscon_clk_init()
903 		en_reg = syscon_vbase + U300_SYSCON_CERR;  in of_u300_syscon_clk_init()
959 		writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);  in mclk_clk_prepare()
960 		val = readw(syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
965 		writew(val, syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
967 		val = readw(syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
972 		writew(val, syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
1010 		u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &  in mclk_clk_recalc_rate()
1101 	reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &  in mclk_clk_set_rate()
1103 	writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);  in mclk_clk_set_rate()
1180 	syscon_vbase = base;  in u300_clk_init()
1183 	val = readw(syscon_vbase + U300_SYSCON_CCR);  in u300_clk_init()
1185 	writew(val, syscon_vbase + U300_SYSCON_CCR);  in u300_clk_init()
1187 	while (!(readw(syscon_vbase + U300_SYSCON_CSR) &  in u300_clk_init()
1191 	val = readw(syscon_vbase + U300_SYSCON_PMCR);  in u300_clk_init()
1193 	writew(val, syscon_vbase + U300_SYSCON_PMCR);  in u300_clk_init()