211 	struct xgene_dev_parameters	param;  member
226 	if (pclk->param.csr_reg != NULL) {  in xgene_clk_enable()
228 		reg = __pa(pclk->param.csr_reg);  in xgene_clk_enable()
230 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
231 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
232 		data |= pclk->param.reg_clk_mask;  in xgene_clk_enable()
233 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
234 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
237 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,  in xgene_clk_enable()
241 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
242 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
243 		data &= ~pclk->param.reg_csr_mask;  in xgene_clk_enable()
244 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
245 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
248 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,  in xgene_clk_enable()
267 	if (pclk->param.csr_reg != NULL) {  in xgene_clk_disable()
270 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
271 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
272 		data |= pclk->param.reg_csr_mask;  in xgene_clk_disable()
273 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
274 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
277 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
278 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
279 		data &= ~pclk->param.reg_clk_mask;  in xgene_clk_disable()
280 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
281 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
293 	if (pclk->param.csr_reg != NULL) {  in xgene_clk_is_enabled()
295 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_is_enabled()
296 					pclk->param.reg_clk_offset);  in xgene_clk_is_enabled()
298 			data & pclk->param.reg_clk_mask ? "enabled" :  in xgene_clk_is_enabled()
302 	if (pclk->param.csr_reg == NULL)  in xgene_clk_is_enabled()
304 	return data & pclk->param.reg_clk_mask ? 1 : 0;  in xgene_clk_is_enabled()
313 	if (pclk->param.divider_reg) {  in xgene_clk_recalc_rate()
314 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_recalc_rate()
315 					pclk->param.reg_divider_offset);  in xgene_clk_recalc_rate()
316 		data >>= pclk->param.reg_divider_shift;  in xgene_clk_recalc_rate()
317 		data &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_recalc_rate()
343 	if (pclk->param.divider_reg) {  in xgene_clk_set_rate()
348 		divider &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_set_rate()
349 		divider <<= pclk->param.reg_divider_shift;  in xgene_clk_set_rate()
352 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_set_rate()
353 				pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
354 		data &= ~((1 << pclk->param.reg_divider_width) - 1);  in xgene_clk_set_rate()
356 		xgene_clk_write(data, pclk->param.divider_reg +  in xgene_clk_set_rate()
357 					pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
377 	if (pclk->param.divider_reg) {  in xgene_clk_round_rate()
422 	apmclk->param = *parameters;  in xgene_register_clk()