51 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)  in clk_pllv3_wait_lock()  argument
54 	u32 val = readl_relaxed(pll->base) & pll->powerdown;  in clk_pllv3_wait_lock()
57 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))  in clk_pllv3_wait_lock()
62 		if (readl_relaxed(pll->base) & BM_PLL_LOCK)  in clk_pllv3_wait_lock()
69 	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;  in clk_pllv3_wait_lock()
74 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_prepare()  local
77 	val = readl_relaxed(pll->base);  in clk_pllv3_prepare()
78 	if (pll->powerup_set)  in clk_pllv3_prepare()
82 	writel_relaxed(val, pll->base);  in clk_pllv3_prepare()
84 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_prepare()
89 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_unprepare()  local
92 	val = readl_relaxed(pll->base);  in clk_pllv3_unprepare()
93 	if (pll->powerup_set)  in clk_pllv3_unprepare()
97 	writel_relaxed(val, pll->base);  in clk_pllv3_unprepare()
103 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_recalc_rate()  local
104 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;  in clk_pllv3_recalc_rate()
121 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_set_rate()  local
131 	val = readl_relaxed(pll->base);  in clk_pllv3_set_rate()
132 	val &= ~(pll->div_mask << pll->div_shift);  in clk_pllv3_set_rate()
133 	val |= (div << pll->div_shift);  in clk_pllv3_set_rate()
134 	writel_relaxed(val, pll->base);  in clk_pllv3_set_rate()
136 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_set_rate()
150 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_recalc_rate()  local
151 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_sys_recalc_rate()
176 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_set_rate()  local
185 	val = readl_relaxed(pll->base);  in clk_pllv3_sys_set_rate()
186 	val &= ~pll->div_mask;  in clk_pllv3_sys_set_rate()
188 	writel_relaxed(val, pll->base);  in clk_pllv3_sys_set_rate()
190 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_sys_set_rate()
204 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_recalc_rate()  local
205 	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);  in clk_pllv3_av_recalc_rate()
206 	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);  in clk_pllv3_av_recalc_rate()
207 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_av_recalc_rate()
239 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_set_rate()  local
255 	val = readl_relaxed(pll->base);  in clk_pllv3_av_set_rate()
256 	val &= ~pll->div_mask;  in clk_pllv3_av_set_rate()
258 	writel_relaxed(val, pll->base);  in clk_pllv3_av_set_rate()
259 	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);  in clk_pllv3_av_set_rate()
260 	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);  in clk_pllv3_av_set_rate()
262 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_av_set_rate()
289 	struct clk_pllv3 *pll;  in imx_clk_pllv3()  local
294 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in imx_clk_pllv3()
295 	if (!pll)  in imx_clk_pllv3()
298 	pll->powerdown = BM_PLL_POWER;  in imx_clk_pllv3()
305 		pll->div_shift = 1;  in imx_clk_pllv3()
308 		pll->powerup_set = true;  in imx_clk_pllv3()
314 		pll->powerdown = IMX7_ENET_PLL_POWER;  in imx_clk_pllv3()
321 	pll->base = base;  in imx_clk_pllv3()
322 	pll->div_mask = div_mask;  in imx_clk_pllv3()
330 	pll->hw.init = &init;  in imx_clk_pllv3()
332 	clk = clk_register(NULL, &pll->hw);  in imx_clk_pllv3()
334 		kfree(pll);  in imx_clk_pllv3()