Lines Matching refs:CGU_REG_CLKGR
29 #define CGU_REG_CLKGR 0x20 macro
124 .gate = { CGU_REG_CLKGR, 10 },
138 .gate = { CGU_REG_CLKGR, 6 },
146 .gate = { CGU_REG_CLKGR, 4 },
153 .gate = { CGU_REG_CLKGR, 7 },
160 .gate = { CGU_REG_CLKGR, 14 },
176 .gate = { CGU_REG_CLKGR, 0 },
182 .gate = { CGU_REG_CLKGR, 15 },
188 .gate = { CGU_REG_CLKGR, 12 },
194 .gate = { CGU_REG_CLKGR, 13 },
200 .gate = { CGU_REG_CLKGR, 8 },
206 .gate = { CGU_REG_CLKGR, 3 },
212 .gate = { CGU_REG_CLKGR, 5 },
252 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
255 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
261 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
264 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
276 clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_suspend()
278 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_suspend()
298 clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_resume()
302 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_resume()