61 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_is_prepared()  local
63 	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;  in mtk_pll_is_prepared()
66 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,  in __mtk_pll_recalc_rate()  argument
69 	int pcwbits = pll->data->pcwbits;  in __mtk_pll_recalc_rate()
90 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,  in mtk_pll_set_rate_regs()  argument
96 	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;  in mtk_pll_set_rate_regs()
99 	val = readl(pll->pd_addr);  in mtk_pll_set_rate_regs()
100 	val &= ~(POSTDIV_MASK << pll->data->pd_shift);  in mtk_pll_set_rate_regs()
101 	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;  in mtk_pll_set_rate_regs()
104 	if (pll->pd_addr != pll->pcw_addr) {  in mtk_pll_set_rate_regs()
105 		writel(val, pll->pd_addr);  in mtk_pll_set_rate_regs()
106 		val = readl(pll->pcw_addr);  in mtk_pll_set_rate_regs()
110 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,  in mtk_pll_set_rate_regs()
111 			pll->data->pcw_shift);  in mtk_pll_set_rate_regs()
112 	val |= pcw << pll->data->pcw_shift;  in mtk_pll_set_rate_regs()
113 	writel(val, pll->pcw_addr);  in mtk_pll_set_rate_regs()
115 	con1 = readl(pll->base_addr + REG_CON1);  in mtk_pll_set_rate_regs()
120 	writel(con1, pll->base_addr + REG_CON1);  in mtk_pll_set_rate_regs()
121 	if (pll->tuner_addr)  in mtk_pll_set_rate_regs()
122 		writel(con1 + 1, pll->tuner_addr);  in mtk_pll_set_rate_regs()
137 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,  in mtk_pll_calc_values()  argument
141 	const struct mtk_pll_div_table *div_table = pll->data->div_table;  in mtk_pll_calc_values()
145 	if (freq > pll->data->fmax)  in mtk_pll_calc_values()
146 		freq = pll->data->fmax;  in mtk_pll_calc_values()
166 	_pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);  in mtk_pll_calc_values()
175 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_set_rate()  local
179 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);  in mtk_pll_set_rate()
180 	mtk_pll_set_rate_regs(pll, pcw, postdiv);  in mtk_pll_set_rate()
188 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_recalc_rate()  local
192 	postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;  in mtk_pll_recalc_rate()
195 	pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;  in mtk_pll_recalc_rate()
196 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);  in mtk_pll_recalc_rate()
198 	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);  in mtk_pll_recalc_rate()
204 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_round_rate()  local
208 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);  in mtk_pll_round_rate()
210 	return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);  in mtk_pll_round_rate()
215 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_prepare()  local
218 	r = readl(pll->pwr_addr) | CON0_PWR_ON;  in mtk_pll_prepare()
219 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
222 	r = readl(pll->pwr_addr) & ~CON0_ISO_EN;  in mtk_pll_prepare()
223 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
226 	r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
227 	r |= pll->data->en_mask;  in mtk_pll_prepare()
228 	writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
230 	if (pll->tuner_addr) {  in mtk_pll_prepare()
231 		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;  in mtk_pll_prepare()
232 		writel(r, pll->tuner_addr);  in mtk_pll_prepare()
237 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_prepare()
238 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
239 		r |= pll->data->rst_bar_mask;  in mtk_pll_prepare()
240 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
248 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_unprepare()  local
251 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_unprepare()
252 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
253 		r &= ~pll->data->rst_bar_mask;  in mtk_pll_unprepare()
254 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
257 	if (pll->tuner_addr) {  in mtk_pll_unprepare()
258 		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;  in mtk_pll_unprepare()
259 		writel(r, pll->tuner_addr);  in mtk_pll_unprepare()
262 	r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
264 	writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
266 	r = readl(pll->pwr_addr) | CON0_ISO_EN;  in mtk_pll_unprepare()
267 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
269 	r = readl(pll->pwr_addr) & ~CON0_PWR_ON;  in mtk_pll_unprepare()
270 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
285 	struct mtk_clk_pll *pll;  in mtk_clk_register_pll()  local
290 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in mtk_clk_register_pll()
291 	if (!pll)  in mtk_clk_register_pll()
294 	pll->base_addr = base + data->reg;  in mtk_clk_register_pll()
295 	pll->pwr_addr = base + data->pwr_reg;  in mtk_clk_register_pll()
296 	pll->pd_addr = base + data->pd_reg;  in mtk_clk_register_pll()
297 	pll->pcw_addr = base + data->pcw_reg;  in mtk_clk_register_pll()
299 		pll->tuner_addr = base + data->tuner_reg;  in mtk_clk_register_pll()
300 	pll->hw.init = &init;  in mtk_clk_register_pll()
301 	pll->data = data;  in mtk_clk_register_pll()
308 	clk = clk_register(NULL, &pll->hw);  in mtk_clk_register_pll()
311 		kfree(pll);  in mtk_clk_register_pll()
330 		const struct mtk_pll_data *pll = &plls[i];  in mtk_clk_register_plls()  local
332 		clk = mtk_clk_register_pll(pll, base);  in mtk_clk_register_plls()
336 					pll->name, PTR_ERR(clk));  in mtk_clk_register_plls()
340 		clk_data->clks[pll->id] = clk;  in mtk_clk_register_plls()