533 static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk,  in lpc18xx_cgu_register_div()  argument
537 	const char *name = clk_src_names[clk->clk_id];  in lpc18xx_cgu_register_div()
540 	clk->div.reg = reg;  in lpc18xx_cgu_register_div()
541 	clk->mux.reg = reg;  in lpc18xx_cgu_register_div()
542 	clk->gate.reg = reg;  in lpc18xx_cgu_register_div()
544 	lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);  in lpc18xx_cgu_register_div()
546 	return clk_register_composite(NULL, name, parents, clk->n_parents,  in lpc18xx_cgu_register_div()
547 				      &clk->mux.hw, &clk_mux_ops,  in lpc18xx_cgu_register_div()
548 				      &clk->div.hw, &clk_divider_ops,  in lpc18xx_cgu_register_div()
549 				      &clk->gate.hw, &lpc18xx_gate_ops, 0);  in lpc18xx_cgu_register_div()
553 static struct clk *lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk,  in lpc18xx_register_base_clk()  argument
557 	const char *name = clk_base_names[clk->clk_id];  in lpc18xx_register_base_clk()
560 	if (clk->n_parents == 0)  in lpc18xx_register_base_clk()
563 	clk->mux.reg = reg;  in lpc18xx_register_base_clk()
564 	clk->gate.reg = reg;  in lpc18xx_register_base_clk()
566 	lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);  in lpc18xx_register_base_clk()
570 		return clk_register_composite(NULL, name, parents, clk->n_parents,  in lpc18xx_register_base_clk()
571 					      &clk->mux.hw, &clk_mux_ops,  in lpc18xx_register_base_clk()
574 	return clk_register_composite(NULL, name, parents, clk->n_parents,  in lpc18xx_register_base_clk()
575 				      &clk->mux.hw, &clk_mux_ops,  in lpc18xx_register_base_clk()
577 				      &clk->gate.hw, &lpc18xx_gate_ops, 0);  in lpc18xx_register_base_clk()
581 static struct clk *lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk *clk,  in lpc18xx_cgu_register_pll()  argument
584 	const char *name = clk_src_names[clk->clk_id];  in lpc18xx_cgu_register_pll()
587 	clk->pll.reg  = base;  in lpc18xx_cgu_register_pll()
588 	clk->mux.reg  = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;  in lpc18xx_cgu_register_pll()
589 	clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;  in lpc18xx_cgu_register_pll()
591 	lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);  in lpc18xx_cgu_register_pll()
593 	return clk_register_composite(NULL, name, parents, clk->n_parents,  in lpc18xx_cgu_register_pll()
594 				      &clk->mux.hw, &clk_mux_ops,  in lpc18xx_cgu_register_pll()
595 				      &clk->pll.hw, clk->pll_ops,  in lpc18xx_cgu_register_pll()
596 				      &clk->gate.hw, &lpc18xx_gate_ops, 0);  in lpc18xx_cgu_register_pll()
603 	struct clk *clk;  in lpc18xx_cgu_register_source_clks()  local
607 	clk = clk_register_fixed_rate(NULL, clk_src_names[CLK_SRC_IRC],  in lpc18xx_cgu_register_source_clks()
609 	if (IS_ERR(clk))  in lpc18xx_cgu_register_source_clks()
614 	clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0],  in lpc18xx_cgu_register_source_clks()
617 	if (IS_ERR(clk))  in lpc18xx_cgu_register_source_clks()
622 		clk = lpc18xx_cgu_register_pll(&lpc18xx_cgu_src_clk_plls[i],  in lpc18xx_cgu_register_source_clks()
624 		if (IS_ERR(clk))  in lpc18xx_cgu_register_source_clks()
630 		clk = lpc18xx_cgu_register_div(&lpc18xx_cgu_src_clk_divs[i],  in lpc18xx_cgu_register_source_clks()
632 		if (IS_ERR(clk))  in lpc18xx_cgu_register_source_clks()
637 static struct clk *clk_base[BASE_CLK_MAX];