81 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)  in pll_readl()  argument
83 	return readl(pll->base + reg);  in pll_readl()
86 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)  in pll_writel()  argument
88 	writel(val, pll->base + reg);  in pll_writel()
91 static inline void pll_lock(struct pistachio_clk_pll *pll)  in pll_lock()  argument
93 	while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))  in pll_lock()
110 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_frac_get_mode()  local
113 	val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;  in pll_frac_get_mode()
119 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_frac_set_mode()  local
122 	val = pll_readl(pll, PLL_CTRL3);  in pll_frac_set_mode()
128 	pll_writel(pll, val, PLL_CTRL3);  in pll_frac_set_mode()
132 pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,  in pll_get_params()  argument
137 	for (i = 0; i < pll->nr_rates; i++) {  in pll_get_params()
138 		if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)  in pll_get_params()
139 			return &pll->rates[i];  in pll_get_params()
148 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_round_rate()  local
151 	for (i = 0; i < pll->nr_rates; i++) {  in pll_round_rate()
152 		if (i > 0 && pll->rates[i].fref == *parent_rate &&  in pll_round_rate()
153 		    pll->rates[i].fout <= rate)  in pll_round_rate()
154 			return pll->rates[i - 1].fout;  in pll_round_rate()
157 	return pll->rates[0].fout;  in pll_round_rate()
162 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_enable()  local
165 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_enable()
168 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_enable()
170 	val = pll_readl(pll, PLL_CTRL4);  in pll_gf40lp_frac_enable()
172 	pll_writel(pll, val, PLL_CTRL4);  in pll_gf40lp_frac_enable()
174 	pll_lock(pll);  in pll_gf40lp_frac_enable()
181 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_disable()  local
184 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_disable()
186 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_disable()
191 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_is_enabled()  local
193 	return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);  in pll_gf40lp_frac_is_enabled()
199 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_set_rate()  local
208 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_frac_set_rate()
229 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
234 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
236 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
258 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
267 		pll_lock(pll);  in pll_gf40lp_frac_set_rate()
275 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_recalc_rate()  local
278 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_recalc_rate()
282 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_recalc_rate()
319 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_enable()  local
322 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_enable()
325 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_enable()
327 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_laint_enable()
329 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_laint_enable()
331 	pll_lock(pll);  in pll_gf40lp_laint_enable()
338 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_disable()  local
341 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_disable()
343 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_disable()
348 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_is_enabled()  local
350 	return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD);  in pll_gf40lp_laint_is_enabled()
356 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_set_rate()  local
365 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_laint_set_rate()
382 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
404 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
407 		pll_lock(pll);  in pll_gf40lp_laint_set_rate()
415 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_recalc_rate()  local
419 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_recalc_rate()
455 	struct pistachio_clk_pll *pll;  in pll_register()  local
459 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in pll_register()
460 	if (!pll)  in pll_register()
483 		kfree(pll);  in pll_register()
487 	pll->hw.init = &init;  in pll_register()
488 	pll->base = base;  in pll_register()
489 	pll->rates = rates;  in pll_register()
490 	pll->nr_rates = nr_rates;  in pll_register()
492 	clk = clk_register(NULL, &pll->hw);  in pll_register()
494 		kfree(pll);  in pll_register()
500 				struct pistachio_pll *pll,  in pistachio_clk_register_pll()  argument
507 		clk = pll_register(pll[i].name, pll[i].parent,  in pistachio_clk_register_pll()
508 				   0, p->base + pll[i].reg_base,  in pistachio_clk_register_pll()
509 				   pll[i].type, pll[i].rates,  in pistachio_clk_register_pll()
510 				   pll[i].nr_rates);  in pistachio_clk_register_pll()
511 		p->clk_data.clks[pll[i].id] = clk;  in pistachio_clk_register_pll()