52 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_is_enabled()  local
56 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in clk_rcg2_is_enabled()
65 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_get_parent()  local
70 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_get_parent()
78 		if (cfg == rcg->parent_map[i].cfg)  in clk_rcg2_get_parent()
87 static int update_config(struct clk_rcg2 *rcg)  in update_config()  argument
91 	struct clk_hw *hw = &rcg->clkr.hw;  in update_config()
94 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in update_config()
101 		ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in update_config()
115 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_set_parent()  local
117 	u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_set_parent()
119 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_rcg2_set_parent()
124 	return update_config(rcg);  in clk_rcg2_set_parent()
155 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_recalc_rate()  local
158 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_recalc_rate()
160 	if (rcg->mnd_width) {  in clk_rcg2_recalc_rate()
161 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_recalc_rate()
162 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);  in clk_rcg2_recalc_rate()
164 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);  in clk_rcg2_recalc_rate()
172 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_recalc_rate()
184 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in _freq_tbl_determine_rate()  local
191 	index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in _freq_tbl_determine_rate()
222 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_determine_rate()  local
224 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req);  in clk_rcg2_determine_rate()
227 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)  in clk_rcg2_configure()  argument
230 	struct clk_hw *hw = &rcg->clkr.hw;  in clk_rcg2_configure()
231 	int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_rcg2_configure()
236 	if (rcg->mnd_width && f->n) {  in clk_rcg2_configure()
237 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_configure()
238 		ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
239 				rcg->cmd_rcgr + M_REG, mask, f->m);  in clk_rcg2_configure()
243 		ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
244 				rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));  in clk_rcg2_configure()
248 		ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
249 				rcg->cmd_rcgr + D_REG, mask, ~f->n);  in clk_rcg2_configure()
254 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_configure()
257 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_configure()
258 	if (rcg->mnd_width && f->n && (f->m != f->n))  in clk_rcg2_configure()
260 	ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
261 			rcg->cmd_rcgr + CFG_REG, mask, cfg);  in clk_rcg2_configure()
265 	return update_config(rcg);  in clk_rcg2_configure()
270 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in __clk_rcg2_set_rate()  local
273 	f = qcom_find_freq(rcg->freq_tbl, rate);  in __clk_rcg2_set_rate()
277 	return clk_rcg2_configure(rcg, f);  in __clk_rcg2_set_rate()
305 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_force_enable()  local
310 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in clk_rcg2_shared_force_enable()
331 	return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in clk_rcg2_shared_force_enable()
338 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_set_rate()  local
341 	rcg->current_freq = rate;  in clk_rcg2_shared_set_rate()
346 	return clk_rcg2_shared_force_enable(hw, rcg->current_freq);  in clk_rcg2_shared_set_rate()
352 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_recalc_rate()  local
354 	return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate);  in clk_rcg2_shared_recalc_rate()
359 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_enable()  local
361 	return clk_rcg2_shared_force_enable(hw, rcg->current_freq);  in clk_rcg2_shared_enable()
366 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_disable()  local
369 	clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0);  in clk_rcg2_shared_disable()
412 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_set_rate()  local
413 	struct freq_tbl f = *rcg->freq_tbl;  in clk_edp_pixel_set_rate()
418 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_set_rate()
434 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_set_rate()
442 		return clk_rcg2_configure(rcg, &f);  in clk_edp_pixel_set_rate()
458 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_determine_rate()  local
459 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_edp_pixel_determine_rate()
463 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_determine_rate()
465 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_edp_pixel_determine_rate()
484 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_determine_rate()
512 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_determine_rate()  local
513 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_byte_determine_rate()
514 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_byte_determine_rate()
516 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_determine_rate()
536 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_set_rate()  local
537 	struct freq_tbl f = *rcg->freq_tbl;  in clk_byte_set_rate()
539 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_set_rate()
546 	return clk_rcg2_configure(rcg, &f);  in clk_byte_set_rate()
570 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte2_determine_rate()  local
572 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte2_determine_rate()
593 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte2_set_rate()  local
597 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte2_set_rate()
605 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_byte2_set_rate()
610 		if (cfg == rcg->parent_map[i].cfg) {  in clk_byte2_set_rate()
611 			f.src = rcg->parent_map[i].src;  in clk_byte2_set_rate()
612 			return clk_rcg2_configure(rcg, &f);  in clk_byte2_set_rate()
671 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_pixel_set_rate()  local
676 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_pixel_set_rate()
680 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_pixel_set_rate()
685 		if (cfg == rcg->parent_map[i].cfg) {  in clk_pixel_set_rate()
686 			f.src = rcg->parent_map[i].src;  in clk_pixel_set_rate()
697 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_pixel_set_rate()
705 		return clk_rcg2_configure(rcg, &f);  in clk_pixel_set_rate()