52 			    struct rockchip_clk_pll *pll, unsigned long rate)  in rockchip_get_pll_settings()  argument
54 	const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;  in rockchip_get_pll_settings()
57 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_get_pll_settings()
68 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_pll_round_rate()  local
69 	const struct rockchip_pll_rate_table *rate_table = pll->rate_table;  in rockchip_pll_round_rate()
73 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_pll_round_rate()
87 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_pll_wait_lock()  argument
94 		ret = regmap_read(grf, pll->lock_offset, &val);  in rockchip_pll_wait_lock()
101 		if (val & BIT(pll->lock_shift))  in rockchip_pll_wait_lock()
129 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3066_pll_get_params()  argument
134 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_get_params()
140 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_get_params()
144 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_get_params()
152 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_recalc_rate()  local
157 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_recalc_rate()
164 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_recalc_rate()
173 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3066_pll_set_params()  argument
176 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3066_pll_set_params()
177 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3066_pll_set_params()
186 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_set_params()
197 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_params()
204 	       pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_set_params()
208 		       pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_set_params()
211 		       pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_set_params()
215 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_params()
219 	ret = rockchip_pll_wait_lock(pll);  in rockchip_rk3066_pll_set_params()
223 		rockchip_rk3066_pll_set_params(pll, &cur);  in rockchip_rk3066_pll_set_params()
235 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_set_rate()  local
250 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_set_rate()
257 	return rockchip_rk3066_pll_set_params(pll, rate);  in rockchip_rk3066_pll_set_rate()
262 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_enable()  local
265 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_enable()
272 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_disable()  local
276 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_disable()
281 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_is_enabled()  local
282 	u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_is_enabled()
289 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_init()  local
294 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3066_pll_init()
298 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_init()
304 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_init()
318 		rockchip_rk3066_pll_set_params(pll, rate);  in rockchip_rk3066_pll_init()
352 	struct rockchip_clk_pll *pll;  in rockchip_clk_register_pll()  local
365 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in rockchip_clk_register_pll()
366 	if (!pll)  in rockchip_clk_register_pll()
370 	pll->pll_mux_ops = &clk_mux_ops;  in rockchip_clk_register_pll()
371 	pll_mux = &pll->pll_mux;  in rockchip_clk_register_pll()
389 	init.ops = pll->pll_mux_ops;  in rockchip_clk_register_pll()
413 		pll->rate_count = len;  in rockchip_clk_register_pll()
414 		pll->rate_table = kmemdup(rate_table,  in rockchip_clk_register_pll()
415 					pll->rate_count *  in rockchip_clk_register_pll()
418 		WARN(!pll->rate_table,  in rockchip_clk_register_pll()
425 		if (!pll->rate_table)  in rockchip_clk_register_pll()
435 	pll->hw.init = &init;  in rockchip_clk_register_pll()
436 	pll->type = pll_type;  in rockchip_clk_register_pll()
437 	pll->reg_base = base + con_offset;  in rockchip_clk_register_pll()
438 	pll->lock_offset = grf_lock_offset;  in rockchip_clk_register_pll()
439 	pll->lock_shift = lock_shift;  in rockchip_clk_register_pll()
440 	pll->flags = clk_pll_flags;  in rockchip_clk_register_pll()
441 	pll->lock = lock;  in rockchip_clk_register_pll()
443 	pll_clk = clk_register(NULL, &pll->hw);  in rockchip_clk_register_pll()
456 	kfree(pll);  in rockchip_clk_register_pll()