Lines Matching refs:ENABLE_PCLK_PERIC1
1560 #define ENABLE_PCLK_PERIC1 0x0904 macro
1571 ENABLE_PCLK_PERIC1,
1661 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1663 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1666 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1668 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1670 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1672 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1674 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1676 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1678 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1680 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),