Lines Matching refs:ENABLE_SCLK_PERIC
1561 #define ENABLE_SCLK_PERIC 0x0A00 macro
1572 ENABLE_SCLK_PERIC,
1684 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1686 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1687 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1689 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1691 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1693 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1695 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1697 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1699 ENABLE_SCLK_PERIC, 12,
1702 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1704 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1707 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1709 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1711 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1712 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1714 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1716 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1719 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1721 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1723 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),