78 	struct clk_pll *clk = to_pllclk(hw);  in pll_clk_recalc_rate()  local
79 	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -  in pll_clk_recalc_rate()
87 		u32 cfg0 = clkc_readl(clk->regofs);  in pll_clk_recalc_rate()
130 	struct clk_pll *clk = to_pllclk(hw);  in pll_clk_set_rate()  local
151 	clkc_writel(reg, clk->regofs);  in pll_clk_set_rate()
153 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
156 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
255 static void usb_pll_clk_disable(struct clk_hw *clk)  in usb_pll_clk_disable()  argument
299 	struct clk_dmn *clk = to_dmnclk(hw);  in dmn_clk_get_parent()  local
300 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_get_parent()
313 	struct clk_dmn *clk = to_dmnclk(hw);  in dmn_clk_set_parent()  local
314 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_set_parent()
321 	clkc_writel(cfg | parent, clk->regofs);  in dmn_clk_set_parent()
323 	while (clkc_readl(clk->regofs) & BIT(3))  in dmn_clk_set_parent()
334 	struct clk_dmn *clk = to_dmnclk(hw);  in dmn_clk_recalc_rate()  local
336 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_recalc_rate()
376 	struct clk_dmn *clk = to_dmnclk(hw);  in dmn_clk_set_rate()  local
392 	reg = clkc_readl(clk->regofs);  in dmn_clk_set_rate()
395 	clkc_writel(reg, clk->regofs);  in dmn_clk_set_rate()
398 	while (clkc_readl(clk->regofs) & BIT(25))  in dmn_clk_set_rate()
408 	struct clk *cur_parent;  in cpu_clk_set_rate()
410 	if (rate == clk_get_rate(clk_pll1.hw.clk)) {  in cpu_clk_set_rate()
411 		ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);  in cpu_clk_set_rate()
415 	if (rate == clk_get_rate(clk_pll2.hw.clk)) {  in cpu_clk_set_rate()
416 		ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);  in cpu_clk_set_rate()
420 	if (rate == clk_get_rate(clk_pll3.hw.clk)) {  in cpu_clk_set_rate()
421 		ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);  in cpu_clk_set_rate()
425 	cur_parent = clk_get_parent(hw->clk);  in cpu_clk_set_rate()
428 	if (cur_parent ==  clk_pll1.hw.clk) {  in cpu_clk_set_rate()
429 		ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);  in cpu_clk_set_rate()
433 	ret2 = clk_set_rate(clk_pll1.hw.clk, rate);  in cpu_clk_set_rate()
435 	ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);  in cpu_clk_set_rate()
636 	struct clk_std *clk = to_stdclk(hw);  in std_clk_is_enabled()  local
638 	bit = clk->enable_bit % 32;  in std_clk_is_enabled()
639 	reg = clk->enable_bit / 32;  in std_clk_is_enabled()
649 	struct clk_std *clk = to_stdclk(hw);  in std_clk_enable()  local
651 	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);  in std_clk_enable()
653 	bit = clk->enable_bit % 32;  in std_clk_enable()
654 	reg = clk->enable_bit / 32;  in std_clk_enable()
666 	struct clk_std *clk = to_stdclk(hw);  in std_clk_disable()  local
668 	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);  in std_clk_disable()
670 	bit = clk->enable_bit % 32;  in std_clk_disable()
671 	reg = clk->enable_bit / 32;  in std_clk_disable()