Lines Matching refs:TEGRA114_CLK_PLL_P
797 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
873 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
1289 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
1290 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
1291 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
1292 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
1303 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
1304 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
1305 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
1306 {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
1307 {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
1310 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1311 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
1316 {TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0},
1317 {TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0},