Lines Matching refs:TEGRA124_CLK_CLK_MAX
1367 {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
1368 {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
1371 {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
1384 {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
1385 {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
1389 {TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0},
1397 {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
1398 {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
1401 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1406 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1410 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1417 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1434 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra124_clock_apply_init_table()
1435 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra124_clock_apply_init_table()
1510 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra132_clock_apply_init_table()
1511 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra132_clock_apply_init_table()
1549 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, in tegra124_132_clock_init_pre()