Lines Matching refs:TEGRA124_CLK_PLL_P
888 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
965 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
1363 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1364 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1365 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
1366 {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
1377 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1378 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1379 {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
1380 {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
1382 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1383 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
1386 {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1395 {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
1396 {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
1405 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1407 {TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},
1408 {TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},
1415 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},