Lines Matching refs:TEGRA20_CLK_PLL_P
432 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
559 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
1028 {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
1041 {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
1042 {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
1043 {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
1044 {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
1045 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
1052 {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
1053 {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
1054 {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
1055 {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
1056 {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
1057 {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
1058 {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
1059 {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
1061 {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
1062 {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},