Lines Matching refs:TEGRA30_CLK_PLL_P
592 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
857 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
1338 {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
1339 {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
1340 {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
1341 {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
1342 {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
1354 {TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
1355 {TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
1356 {TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
1362 {TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
1363 {TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
1364 {TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
1365 {TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
1366 {TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
1367 {TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
1369 {TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
1370 {TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},