Lines Matching refs:clk_register_divider
149 clk = clk_register_divider(NULL, div0_name, mux_name, in zynq_clk_register_fclk()
153 clk = clk_register_divider(NULL, div1_name, div0_name, in zynq_clk_register_fclk()
206 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, in zynq_clk_register_periph_clk()
295 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, in zynq_clk_setup()
339 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, in zynq_clk_setup()
345 clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, in zynq_clk_setup()
352 clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, in zynq_clk_setup()
355 clk = clk_register_divider(NULL, "dci_div1", "dci_div0", in zynq_clk_setup()
403 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, in zynq_clk_setup()
406 clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", in zynq_clk_setup()
428 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, in zynq_clk_setup()
431 clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", in zynq_clk_setup()
460 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, in zynq_clk_setup()
463 clk = clk_register_divider(NULL, "can_div1", "can_div0", in zynq_clk_setup()
500 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, in zynq_clk_setup()