Lines Matching refs:rdmsrl
277 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); in update_turbo_state()
288 rdmsrl(MSR_HWP_CAPABILITIES, cap); in intel_pstate_hwp_set()
535 rdmsrl(ATOM_RATIOS, value); in atom_get_min_pstate()
543 rdmsrl(ATOM_RATIOS, value); in atom_get_max_pstate()
551 rdmsrl(ATOM_TURBO_RATIOS, value); in atom_get_turbo_pstate()
588 rdmsrl(MSR_FSB_FREQ, value); in silvermont_get_scaling()
604 rdmsrl(MSR_FSB_FREQ, value); in airmont_get_scaling()
615 rdmsrl(ATOM_VIDS, value); in atom_get_vid()
623 rdmsrl(ATOM_TURBO_VIDS, value); in atom_get_vid()
631 rdmsrl(MSR_PLATFORM_INFO, value); in core_get_min_pstate()
639 rdmsrl(MSR_PLATFORM_INFO, value); in core_get_max_pstate_physical()
650 rdmsrl(MSR_PLATFORM_INFO, plat_info); in core_get_max_pstate()
693 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); in core_get_turbo_pstate()
722 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); in knl_get_turbo_pstate()
888 rdmsrl(MSR_IA32_APERF, aperf); in intel_pstate_sample()
889 rdmsrl(MSR_IA32_MPERF, mperf); in intel_pstate_sample()
1335 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); in intel_pstate_platform_pwr_mgmt_exists()