Lines Matching refs:bank
26 #define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00) argument
27 #define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04) argument
28 #define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08) argument
29 #define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c) argument
30 #define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10) argument
31 #define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14) argument
32 #define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18) argument
33 #define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c) argument
70 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc); in brcmstb_gpio_gc_to_priv() local
71 return bank->parent_priv; in brcmstb_gpio_gc_to_priv()
74 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, in brcmstb_gpio_set_imask() argument
77 struct bgpio_chip *bgc = &bank->bgc; in brcmstb_gpio_set_imask()
78 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_set_imask()
84 imask = bgc->read_reg(priv->reg_base + GIO_MASK(bank->id)); in brcmstb_gpio_set_imask()
89 bgc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); in brcmstb_gpio_set_imask()
98 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc); in brcmstb_gpio_irq_mask() local
100 brcmstb_gpio_set_imask(bank, d->hwirq, false); in brcmstb_gpio_irq_mask()
106 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc); in brcmstb_gpio_irq_unmask() local
108 brcmstb_gpio_set_imask(bank, d->hwirq, true); in brcmstb_gpio_irq_unmask()
114 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc); in brcmstb_gpio_irq_set_type() local
115 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_type()
152 spin_lock_irqsave(&bank->bgc.lock, flags); in brcmstb_gpio_irq_set_type()
154 iedge_config = bank->bgc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
155 GIO_EC(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
156 iedge_insensitive = bank->bgc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
157 GIO_EI(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
158 ilevel = bank->bgc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
159 GIO_LEVEL(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
161 bank->bgc.write_reg(priv->reg_base + GIO_EC(bank->id), in brcmstb_gpio_irq_set_type()
163 bank->bgc.write_reg(priv->reg_base + GIO_EI(bank->id), in brcmstb_gpio_irq_set_type()
165 bank->bgc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), in brcmstb_gpio_irq_set_type()
168 spin_unlock_irqrestore(&bank->bgc.lock, flags); in brcmstb_gpio_irq_set_type()
210 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) in brcmstb_gpio_irq_bank_handler() argument
212 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_bank_handler()
213 struct irq_domain *irq_domain = bank->bgc.gc.irqdomain; in brcmstb_gpio_irq_bank_handler()
218 spin_lock_irqsave(&bank->bgc.lock, flags); in brcmstb_gpio_irq_bank_handler()
219 while ((status = bank->bgc.read_reg(reg_base + GIO_STAT(bank->id)) & in brcmstb_gpio_irq_bank_handler()
220 bank->bgc.read_reg(reg_base + GIO_MASK(bank->id)))) { in brcmstb_gpio_irq_bank_handler()
224 u32 stat = bank->bgc.read_reg(reg_base + in brcmstb_gpio_irq_bank_handler()
225 GIO_STAT(bank->id)); in brcmstb_gpio_irq_bank_handler()
226 if (bit >= bank->width) in brcmstb_gpio_irq_bank_handler()
229 bank->id, bit); in brcmstb_gpio_irq_bank_handler()
230 bank->bgc.write_reg(reg_base + GIO_STAT(bank->id), in brcmstb_gpio_irq_bank_handler()
235 spin_unlock_irqrestore(&bank->bgc.lock, flags); in brcmstb_gpio_irq_bank_handler()
251 struct brcmstb_gpio_bank *bank = in brcmstb_gpio_irq_handler() local
253 brcmstb_gpio_irq_bank_handler(bank); in brcmstb_gpio_irq_handler()
292 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_remove() local
305 bank = list_entry(pos, struct brcmstb_gpio_bank, node); in brcmstb_gpio_remove()
306 ret = bgpio_remove(&bank->bgc); in brcmstb_gpio_remove()
323 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc); in brcmstb_gpio_of_xlate() local
338 if (unlikely(offset >= bank->width)) { in brcmstb_gpio_of_xlate()
352 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_irq_setup() argument
354 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_setup()
358 bank->irq_chip.name = dev_name(dev); in brcmstb_gpio_irq_setup()
359 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask; in brcmstb_gpio_irq_setup()
360 bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask; in brcmstb_gpio_irq_setup()
361 bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type; in brcmstb_gpio_irq_setup()
364 bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; in brcmstb_gpio_irq_setup()
399 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake; in brcmstb_gpio_irq_setup()
401 gpiochip_irqchip_add(&bank->bgc.gc, &bank->irq_chip, 0, in brcmstb_gpio_irq_setup()
403 gpiochip_set_chained_irqchip(&bank->bgc.gc, &bank->irq_chip, in brcmstb_gpio_irq_setup()
453 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_probe() local
457 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); in brcmstb_gpio_probe()
458 if (!bank) { in brcmstb_gpio_probe()
463 bank->parent_priv = priv; in brcmstb_gpio_probe()
464 bank->id = num_banks; in brcmstb_gpio_probe()
469 bank->width = bank_width; in brcmstb_gpio_probe()
476 bgc = &bank->bgc; in brcmstb_gpio_probe()
478 reg_base + GIO_DATA(bank->id), in brcmstb_gpio_probe()
480 reg_base + GIO_IODIR(bank->id), 0); in brcmstb_gpio_probe()
500 bank->bgc.write_reg(reg_base + GIO_MASK(bank->id), 0); in brcmstb_gpio_probe()
505 bank->id); in brcmstb_gpio_probe()
511 err = brcmstb_gpio_irq_setup(pdev, bank); in brcmstb_gpio_probe()
516 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, in brcmstb_gpio_probe()
517 gc->base, gc->ngpio, bank->width); in brcmstb_gpio_probe()
520 list_add(&bank->node, &priv->bank_list); in brcmstb_gpio_probe()