80 	void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
88 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)  argument
99 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,  in omap_set_gpio_direction()  argument
102 	void __iomem *reg = bank->base;  in omap_set_gpio_direction()
105 	reg += bank->regs->direction;  in omap_set_gpio_direction()
112 	bank->context.oe = l;  in omap_set_gpio_direction()
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,  in omap_set_gpio_dataout_reg()  argument
120 	void __iomem *reg = bank->base;  in omap_set_gpio_dataout_reg()
124 		reg += bank->regs->set_dataout;  in omap_set_gpio_dataout_reg()
125 		bank->context.dataout |= l;  in omap_set_gpio_dataout_reg()
127 		reg += bank->regs->clr_dataout;  in omap_set_gpio_dataout_reg()
128 		bank->context.dataout &= ~l;  in omap_set_gpio_dataout_reg()
135 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,  in omap_set_gpio_dataout_mask()  argument
138 	void __iomem *reg = bank->base + bank->regs->dataout;  in omap_set_gpio_dataout_mask()
148 	bank->context.dataout = l;  in omap_set_gpio_dataout_mask()
151 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)  in omap_get_gpio_datain()  argument
153 	void __iomem *reg = bank->base + bank->regs->datain;  in omap_get_gpio_datain()
158 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)  in omap_get_gpio_dataout()  argument
160 	void __iomem *reg = bank->base + bank->regs->dataout;  in omap_get_gpio_dataout()
177 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)  in omap_gpio_dbck_enable()  argument
179 	if (bank->dbck_enable_mask && !bank->dbck_enabled) {  in omap_gpio_dbck_enable()
180 		clk_enable(bank->dbck);  in omap_gpio_dbck_enable()
181 		bank->dbck_enabled = true;  in omap_gpio_dbck_enable()
183 		writel_relaxed(bank->dbck_enable_mask,  in omap_gpio_dbck_enable()
184 			     bank->base + bank->regs->debounce_en);  in omap_gpio_dbck_enable()
188 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)  in omap_gpio_dbck_disable()  argument
190 	if (bank->dbck_enable_mask && bank->dbck_enabled) {  in omap_gpio_dbck_disable()
196 		writel_relaxed(0, bank->base + bank->regs->debounce_en);  in omap_gpio_dbck_disable()
198 		clk_disable(bank->dbck);  in omap_gpio_dbck_disable()
199 		bank->dbck_enabled = false;  in omap_gpio_dbck_disable()
213 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,  in omap2_set_gpio_debounce()  argument
221 	if (!bank->dbck_flag)  in omap2_set_gpio_debounce()
231 	clk_enable(bank->dbck);  in omap2_set_gpio_debounce()
232 	reg = bank->base + bank->regs->debounce;  in omap2_set_gpio_debounce()
235 	reg = bank->base + bank->regs->debounce_en;  in omap2_set_gpio_debounce()
242 	bank->dbck_enable_mask = val;  in omap2_set_gpio_debounce()
245 	clk_disable(bank->dbck);  in omap2_set_gpio_debounce()
254 	omap_gpio_dbck_enable(bank);  in omap2_set_gpio_debounce()
255 	if (bank->dbck_enable_mask) {  in omap2_set_gpio_debounce()
256 		bank->context.debounce = debounce;  in omap2_set_gpio_debounce()
257 		bank->context.debounce_en = val;  in omap2_set_gpio_debounce()
271 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)  in omap_clear_gpio_debounce()  argument
275 	if (!bank->dbck_flag)  in omap_clear_gpio_debounce()
278 	if (!(bank->dbck_enable_mask & gpio_bit))  in omap_clear_gpio_debounce()
281 	bank->dbck_enable_mask &= ~gpio_bit;  in omap_clear_gpio_debounce()
282 	bank->context.debounce_en &= ~gpio_bit;  in omap_clear_gpio_debounce()
283         writel_relaxed(bank->context.debounce_en,  in omap_clear_gpio_debounce()
284 		     bank->base + bank->regs->debounce_en);  in omap_clear_gpio_debounce()
286 	if (!bank->dbck_enable_mask) {  in omap_clear_gpio_debounce()
287 		bank->context.debounce = 0;  in omap_clear_gpio_debounce()
288 		writel_relaxed(bank->context.debounce, bank->base +  in omap_clear_gpio_debounce()
289 			     bank->regs->debounce);  in omap_clear_gpio_debounce()
290 		clk_disable(bank->dbck);  in omap_clear_gpio_debounce()
291 		bank->dbck_enabled = false;  in omap_clear_gpio_debounce()
295 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,  in omap_set_gpio_trigger()  argument
298 	void __iomem *base = bank->base;  in omap_set_gpio_trigger()
301 	omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,  in omap_set_gpio_trigger()
303 	omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,  in omap_set_gpio_trigger()
305 	omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,  in omap_set_gpio_trigger()
307 	omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,  in omap_set_gpio_trigger()
310 	bank->context.leveldetect0 =  in omap_set_gpio_trigger()
311 			readl_relaxed(bank->base + bank->regs->leveldetect0);  in omap_set_gpio_trigger()
312 	bank->context.leveldetect1 =  in omap_set_gpio_trigger()
313 			readl_relaxed(bank->base + bank->regs->leveldetect1);  in omap_set_gpio_trigger()
314 	bank->context.risingdetect =  in omap_set_gpio_trigger()
315 			readl_relaxed(bank->base + bank->regs->risingdetect);  in omap_set_gpio_trigger()
316 	bank->context.fallingdetect =  in omap_set_gpio_trigger()
317 			readl_relaxed(bank->base + bank->regs->fallingdetect);  in omap_set_gpio_trigger()
319 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {  in omap_set_gpio_trigger()
320 		omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);  in omap_set_gpio_trigger()
321 		bank->context.wake_en =  in omap_set_gpio_trigger()
322 			readl_relaxed(bank->base + bank->regs->wkup_en);  in omap_set_gpio_trigger()
326 	if (!bank->regs->irqctrl) {  in omap_set_gpio_trigger()
328 		if (bank->non_wakeup_gpios) {  in omap_set_gpio_trigger()
329 			if (!(bank->non_wakeup_gpios & gpio_bit))  in omap_set_gpio_trigger()
340 			bank->enabled_non_wakeup_gpios |= gpio_bit;  in omap_set_gpio_trigger()
342 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;  in omap_set_gpio_trigger()
346 	bank->level_mask =  in omap_set_gpio_trigger()
347 		readl_relaxed(bank->base + bank->regs->leveldetect0) |  in omap_set_gpio_trigger()
348 		readl_relaxed(bank->base + bank->regs->leveldetect1);  in omap_set_gpio_trigger()
356 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)  in omap_toggle_gpio_edge_triggering()  argument
358 	void __iomem *reg = bank->base;  in omap_toggle_gpio_edge_triggering()
361 	if (!bank->regs->irqctrl)  in omap_toggle_gpio_edge_triggering()
364 	reg += bank->regs->irqctrl;  in omap_toggle_gpio_edge_triggering()
375 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}  in omap_toggle_gpio_edge_triggering()  argument
378 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,  in omap_set_gpio_triggering()  argument
381 	void __iomem *reg = bank->base;  in omap_set_gpio_triggering()
382 	void __iomem *base = bank->base;  in omap_set_gpio_triggering()
385 	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {  in omap_set_gpio_triggering()
386 		omap_set_gpio_trigger(bank, gpio, trigger);  in omap_set_gpio_triggering()
387 	} else if (bank->regs->irqctrl) {  in omap_set_gpio_triggering()
388 		reg += bank->regs->irqctrl;  in omap_set_gpio_triggering()
392 			bank->toggle_mask |= BIT(gpio);  in omap_set_gpio_triggering()
401 	} else if (bank->regs->edgectrl1) {  in omap_set_gpio_triggering()
403 			reg += bank->regs->edgectrl2;  in omap_set_gpio_triggering()
405 			reg += bank->regs->edgectrl1;  in omap_set_gpio_triggering()
416 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);  in omap_set_gpio_triggering()
417 		bank->context.wake_en =  in omap_set_gpio_triggering()
418 			readl_relaxed(bank->base + bank->regs->wkup_en);  in omap_set_gpio_triggering()
424 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)  in omap_enable_gpio_module()  argument
426 	if (bank->regs->pinctrl) {  in omap_enable_gpio_module()
427 		void __iomem *reg = bank->base + bank->regs->pinctrl;  in omap_enable_gpio_module()
433 	if (bank->regs->ctrl && !BANK_USED(bank)) {  in omap_enable_gpio_module()
434 		void __iomem *reg = bank->base + bank->regs->ctrl;  in omap_enable_gpio_module()
441 		bank->context.ctrl = ctrl;  in omap_enable_gpio_module()
445 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)  in omap_disable_gpio_module()  argument
447 	void __iomem *base = bank->base;  in omap_disable_gpio_module()
449 	if (bank->regs->wkup_en &&  in omap_disable_gpio_module()
450 	    !LINE_USED(bank->mod_usage, offset) &&  in omap_disable_gpio_module()
451 	    !LINE_USED(bank->irq_usage, offset)) {  in omap_disable_gpio_module()
453 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);  in omap_disable_gpio_module()
454 		bank->context.wake_en =  in omap_disable_gpio_module()
455 			readl_relaxed(bank->base + bank->regs->wkup_en);  in omap_disable_gpio_module()
458 	if (bank->regs->ctrl && !BANK_USED(bank)) {  in omap_disable_gpio_module()
459 		void __iomem *reg = bank->base + bank->regs->ctrl;  in omap_disable_gpio_module()
466 		bank->context.ctrl = ctrl;  in omap_disable_gpio_module()
470 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)  in omap_gpio_is_input()  argument
472 	void __iomem *reg = bank->base + bank->regs->direction;  in omap_gpio_is_input()
477 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)  in omap_gpio_init_irq()  argument
479 	if (!LINE_USED(bank->mod_usage, offset)) {  in omap_gpio_init_irq()
480 		omap_enable_gpio_module(bank, offset);  in omap_gpio_init_irq()
481 		omap_set_gpio_direction(bank, offset, 1);  in omap_gpio_init_irq()
483 	bank->irq_usage |= BIT(offset);  in omap_gpio_init_irq()
488 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_irq_type()  local
496 	if (!bank->regs->leveldetect0 &&  in omap_gpio_irq_type()
500 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_irq_type()
501 	retval = omap_set_gpio_triggering(bank, offset, type);  in omap_gpio_irq_type()
503 		raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_type()
506 	omap_gpio_init_irq(bank, offset);  in omap_gpio_irq_type()
507 	if (!omap_gpio_is_input(bank, offset)) {  in omap_gpio_irq_type()
508 		raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_type()
512 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_type()
525 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)  in omap_clear_gpio_irqbank()  argument
527 	void __iomem *reg = bank->base;  in omap_clear_gpio_irqbank()
529 	reg += bank->regs->irqstatus;  in omap_clear_gpio_irqbank()
533 	if (bank->regs->irqstatus2) {  in omap_clear_gpio_irqbank()
534 		reg = bank->base + bank->regs->irqstatus2;  in omap_clear_gpio_irqbank()
542 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,  in omap_clear_gpio_irqstatus()  argument
545 	omap_clear_gpio_irqbank(bank, BIT(offset));  in omap_clear_gpio_irqstatus()
548 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)  in omap_get_gpio_irqbank_mask()  argument
550 	void __iomem *reg = bank->base;  in omap_get_gpio_irqbank_mask()
552 	u32 mask = (BIT(bank->width)) - 1;  in omap_get_gpio_irqbank_mask()
554 	reg += bank->regs->irqenable;  in omap_get_gpio_irqbank_mask()
556 	if (bank->regs->irqenable_inv)  in omap_get_gpio_irqbank_mask()
562 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)  in omap_enable_gpio_irqbank()  argument
564 	void __iomem *reg = bank->base;  in omap_enable_gpio_irqbank()
567 	if (bank->regs->set_irqenable) {  in omap_enable_gpio_irqbank()
568 		reg += bank->regs->set_irqenable;  in omap_enable_gpio_irqbank()
570 		bank->context.irqenable1 |= gpio_mask;  in omap_enable_gpio_irqbank()
572 		reg += bank->regs->irqenable;  in omap_enable_gpio_irqbank()
574 		if (bank->regs->irqenable_inv)  in omap_enable_gpio_irqbank()
578 		bank->context.irqenable1 = l;  in omap_enable_gpio_irqbank()
584 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)  in omap_disable_gpio_irqbank()  argument
586 	void __iomem *reg = bank->base;  in omap_disable_gpio_irqbank()
589 	if (bank->regs->clr_irqenable) {  in omap_disable_gpio_irqbank()
590 		reg += bank->regs->clr_irqenable;  in omap_disable_gpio_irqbank()
592 		bank->context.irqenable1 &= ~gpio_mask;  in omap_disable_gpio_irqbank()
594 		reg += bank->regs->irqenable;  in omap_disable_gpio_irqbank()
596 		if (bank->regs->irqenable_inv)  in omap_disable_gpio_irqbank()
600 		bank->context.irqenable1 = l;  in omap_disable_gpio_irqbank()
606 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,  in omap_set_gpio_irqenable()  argument
610 		omap_enable_gpio_irqbank(bank, BIT(offset));  in omap_set_gpio_irqenable()
612 		omap_disable_gpio_irqbank(bank, BIT(offset));  in omap_set_gpio_irqenable()
623 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,  in omap_set_gpio_wakeup()  argument
629 	if (bank->non_wakeup_gpios & gpio_bit) {  in omap_set_gpio_wakeup()
630 		dev_err(bank->dev,  in omap_set_gpio_wakeup()
636 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_set_gpio_wakeup()
638 		bank->context.wake_en |= gpio_bit;  in omap_set_gpio_wakeup()
640 		bank->context.wake_en &= ~gpio_bit;  in omap_set_gpio_wakeup()
642 	writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);  in omap_set_gpio_wakeup()
643 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_set_gpio_wakeup()
651 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_wake_enable()  local
655 	ret = omap_set_gpio_wakeup(bank, offset, enable);  in omap_gpio_wake_enable()
657 		ret = irq_set_irq_wake(bank->irq, enable);  in omap_gpio_wake_enable()
664 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_request()  local
671 	if (!BANK_USED(bank))  in omap_gpio_request()
672 		pm_runtime_get_sync(bank->dev);  in omap_gpio_request()
674 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_request()
675 	omap_enable_gpio_module(bank, offset);  in omap_gpio_request()
676 	bank->mod_usage |= BIT(offset);  in omap_gpio_request()
677 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_request()
684 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_free()  local
687 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_free()
688 	bank->mod_usage &= ~(BIT(offset));  in omap_gpio_free()
689 	if (!LINE_USED(bank->irq_usage, offset)) {  in omap_gpio_free()
690 		omap_set_gpio_direction(bank, offset, 1);  in omap_gpio_free()
691 		omap_clear_gpio_debounce(bank, offset);  in omap_gpio_free()
693 	omap_disable_gpio_module(bank, offset);  in omap_gpio_free()
694 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_free()
700 	if (!BANK_USED(bank))  in omap_gpio_free()
701 		pm_runtime_put(bank->dev);  in omap_gpio_free()
718 	struct gpio_bank *bank = gpiobank;  in omap_gpio_irq_handler()  local
722 	isr_reg = bank->base + bank->regs->irqstatus;  in omap_gpio_irq_handler()
726 	pm_runtime_get_sync(bank->dev);  in omap_gpio_irq_handler()
732 		raw_spin_lock_irqsave(&bank->lock, lock_flags);  in omap_gpio_irq_handler()
734 		enabled = omap_get_gpio_irqbank_mask(bank);  in omap_gpio_irq_handler()
737 		if (bank->level_mask)  in omap_gpio_irq_handler()
738 			level_mask = bank->level_mask & enabled;  in omap_gpio_irq_handler()
743 		omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);  in omap_gpio_irq_handler()
744 		omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);  in omap_gpio_irq_handler()
745 		omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);  in omap_gpio_irq_handler()
747 		raw_spin_unlock_irqrestore(&bank->lock, lock_flags);  in omap_gpio_irq_handler()
756 			raw_spin_lock_irqsave(&bank->lock, lock_flags);  in omap_gpio_irq_handler()
764 			if (bank->toggle_mask & (BIT(bit)))  in omap_gpio_irq_handler()
765 				omap_toggle_gpio_edge_triggering(bank, bit);  in omap_gpio_irq_handler()
767 			raw_spin_unlock_irqrestore(&bank->lock, lock_flags);  in omap_gpio_irq_handler()
769 			raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);  in omap_gpio_irq_handler()
771 			generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,  in omap_gpio_irq_handler()
774 			raw_spin_unlock_irqrestore(&bank->wa_lock,  in omap_gpio_irq_handler()
779 	pm_runtime_put(bank->dev);  in omap_gpio_irq_handler()
785 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_irq_startup()  local
789 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_irq_startup()
791 	if (!LINE_USED(bank->mod_usage, offset))  in omap_gpio_irq_startup()
792 		omap_set_gpio_direction(bank, offset, 1);  in omap_gpio_irq_startup()
793 	else if (!omap_gpio_is_input(bank, offset))  in omap_gpio_irq_startup()
795 	omap_enable_gpio_module(bank, offset);  in omap_gpio_irq_startup()
796 	bank->irq_usage |= BIT(offset);  in omap_gpio_irq_startup()
798 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_startup()
803 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_startup()
809 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_irq_shutdown()  local
813 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_irq_shutdown()
814 	bank->irq_usage &= ~(BIT(offset));  in omap_gpio_irq_shutdown()
815 	omap_set_gpio_irqenable(bank, offset, 0);  in omap_gpio_irq_shutdown()
816 	omap_clear_gpio_irqstatus(bank, offset);  in omap_gpio_irq_shutdown()
817 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);  in omap_gpio_irq_shutdown()
818 	if (!LINE_USED(bank->mod_usage, offset))  in omap_gpio_irq_shutdown()
819 		omap_clear_gpio_debounce(bank, offset);  in omap_gpio_irq_shutdown()
820 	omap_disable_gpio_module(bank, offset);  in omap_gpio_irq_shutdown()
821 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_shutdown()
826 	struct gpio_bank *bank = omap_irq_data_get_bank(data);  in omap_gpio_irq_bus_lock()  local
828 	if (!BANK_USED(bank))  in omap_gpio_irq_bus_lock()
829 		pm_runtime_get_sync(bank->dev);  in omap_gpio_irq_bus_lock()
834 	struct gpio_bank *bank = omap_irq_data_get_bank(data);  in gpio_irq_bus_sync_unlock()  local
840 	if (!BANK_USED(bank))  in gpio_irq_bus_sync_unlock()
841 		pm_runtime_put(bank->dev);  in gpio_irq_bus_sync_unlock()
846 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_ack_irq()  local
849 	omap_clear_gpio_irqstatus(bank, offset);  in omap_gpio_ack_irq()
854 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_mask_irq()  local
858 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_mask_irq()
859 	omap_set_gpio_irqenable(bank, offset, 0);  in omap_gpio_mask_irq()
860 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);  in omap_gpio_mask_irq()
861 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_mask_irq()
866 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_unmask_irq()  local
871 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_unmask_irq()
873 		omap_set_gpio_triggering(bank, offset, trigger);  in omap_gpio_unmask_irq()
877 	if (bank->level_mask & BIT(offset)) {  in omap_gpio_unmask_irq()
878 		omap_set_gpio_irqenable(bank, offset, 0);  in omap_gpio_unmask_irq()
879 		omap_clear_gpio_irqstatus(bank, offset);  in omap_gpio_unmask_irq()
882 	omap_set_gpio_irqenable(bank, offset, 1);  in omap_gpio_unmask_irq()
883 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_unmask_irq()
891 	struct gpio_bank	*bank = platform_get_drvdata(pdev);  in omap_mpuio_suspend_noirq()  local
892 	void __iomem		*mask_reg = bank->base +  in omap_mpuio_suspend_noirq()
893 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;  in omap_mpuio_suspend_noirq()
896 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_mpuio_suspend_noirq()
897 	writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);  in omap_mpuio_suspend_noirq()
898 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_mpuio_suspend_noirq()
906 	struct gpio_bank	*bank = platform_get_drvdata(pdev);  in omap_mpuio_resume_noirq()  local
907 	void __iomem		*mask_reg = bank->base +  in omap_mpuio_resume_noirq()
908 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;  in omap_mpuio_resume_noirq()
911 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_mpuio_resume_noirq()
912 	writel_relaxed(bank->context.wake_en, mask_reg);  in omap_mpuio_resume_noirq()
913 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_mpuio_resume_noirq()
940 static inline void omap_mpuio_init(struct gpio_bank *bank)  in omap_mpuio_init()  argument
942 	platform_set_drvdata(&omap_mpuio_device, bank);  in omap_mpuio_init()
952 	struct gpio_bank *bank;  in omap_gpio_get_direction()  local
957 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_get_direction()
958 	reg = bank->base + bank->regs->direction;  in omap_gpio_get_direction()
959 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_get_direction()
961 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_get_direction()
967 	struct gpio_bank *bank;  in omap_gpio_input()  local
970 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_input()
971 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_input()
972 	omap_set_gpio_direction(bank, offset, 1);  in omap_gpio_input()
973 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_input()
979 	struct gpio_bank *bank;  in omap_gpio_get()  local
981 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_get()
983 	if (omap_gpio_is_input(bank, offset))  in omap_gpio_get()
984 		return omap_get_gpio_datain(bank, offset);  in omap_gpio_get()
986 		return omap_get_gpio_dataout(bank, offset);  in omap_gpio_get()
991 	struct gpio_bank *bank;  in omap_gpio_output()  local
994 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_output()
995 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_output()
996 	bank->set_dataout(bank, offset, value);  in omap_gpio_output()
997 	omap_set_gpio_direction(bank, offset, 0);  in omap_gpio_output()
998 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_output()
1005 	struct gpio_bank *bank;  in omap_gpio_debounce()  local
1008 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_debounce()
1010 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_debounce()
1011 	omap2_set_gpio_debounce(bank, offset, debounce);  in omap_gpio_debounce()
1012 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_debounce()
1019 	struct gpio_bank *bank;  in omap_gpio_set()  local
1022 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_set()
1023 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_set()
1024 	bank->set_dataout(bank, offset, value);  in omap_gpio_set()
1025 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_set()
1030 static void __init omap_gpio_show_rev(struct gpio_bank *bank)  in omap_gpio_show_rev()  argument
1035 	if (called || bank->regs->revision == USHRT_MAX)  in omap_gpio_show_rev()
1038 	rev = readw_relaxed(bank->base + bank->regs->revision);  in omap_gpio_show_rev()
1045 static void omap_gpio_mod_init(struct gpio_bank *bank)  in omap_gpio_mod_init()  argument
1047 	void __iomem *base = bank->base;  in omap_gpio_mod_init()
1050 	if (bank->width == 16)  in omap_gpio_mod_init()
1053 	if (bank->is_mpuio) {  in omap_gpio_mod_init()
1054 		writel_relaxed(l, bank->base + bank->regs->irqenable);  in omap_gpio_mod_init()
1058 	omap_gpio_rmw(base, bank->regs->irqenable, l,  in omap_gpio_mod_init()
1059 		      bank->regs->irqenable_inv);  in omap_gpio_mod_init()
1060 	omap_gpio_rmw(base, bank->regs->irqstatus, l,  in omap_gpio_mod_init()
1061 		      !bank->regs->irqenable_inv);  in omap_gpio_mod_init()
1062 	if (bank->regs->debounce_en)  in omap_gpio_mod_init()
1063 		writel_relaxed(0, base + bank->regs->debounce_en);  in omap_gpio_mod_init()
1066 	bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);  in omap_gpio_mod_init()
1068 	if (bank->regs->ctrl)  in omap_gpio_mod_init()
1069 		writel_relaxed(0, base + bank->regs->ctrl);  in omap_gpio_mod_init()
1072 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)  in omap_gpio_chip_init()  argument
1082 	bank->chip.request = omap_gpio_request;  in omap_gpio_chip_init()
1083 	bank->chip.free = omap_gpio_free;  in omap_gpio_chip_init()
1084 	bank->chip.get_direction = omap_gpio_get_direction;  in omap_gpio_chip_init()
1085 	bank->chip.direction_input = omap_gpio_input;  in omap_gpio_chip_init()
1086 	bank->chip.get = omap_gpio_get;  in omap_gpio_chip_init()
1087 	bank->chip.direction_output = omap_gpio_output;  in omap_gpio_chip_init()
1088 	bank->chip.set_debounce = omap_gpio_debounce;  in omap_gpio_chip_init()
1089 	bank->chip.set = omap_gpio_set;  in omap_gpio_chip_init()
1090 	if (bank->is_mpuio) {  in omap_gpio_chip_init()
1091 		bank->chip.label = "mpuio";  in omap_gpio_chip_init()
1092 		if (bank->regs->wkup_en)  in omap_gpio_chip_init()
1093 			bank->chip.dev = &omap_mpuio_device.dev;  in omap_gpio_chip_init()
1094 		bank->chip.base = OMAP_MPUIO(0);  in omap_gpio_chip_init()
1096 		bank->chip.label = "gpio";  in omap_gpio_chip_init()
1097 		bank->chip.base = gpio;  in omap_gpio_chip_init()
1099 	bank->chip.ngpio = bank->width;  in omap_gpio_chip_init()
1101 	ret = gpiochip_add(&bank->chip);  in omap_gpio_chip_init()
1103 		dev_err(bank->dev, "Could not register gpio chip %d\n", ret);  in omap_gpio_chip_init()
1107 	if (!bank->is_mpuio)  in omap_gpio_chip_init()
1108 		gpio += bank->width;  in omap_gpio_chip_init()
1115 	irq_base = irq_alloc_descs(-1, 0, bank->width, 0);  in omap_gpio_chip_init()
1117 		dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");  in omap_gpio_chip_init()
1123 	if (bank->is_mpuio) {  in omap_gpio_chip_init()
1125 		if (!bank->regs->wkup_en)  in omap_gpio_chip_init()
1129 	ret = gpiochip_irqchip_add(&bank->chip, irqc,  in omap_gpio_chip_init()
1134 		dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);  in omap_gpio_chip_init()
1135 		gpiochip_remove(&bank->chip);  in omap_gpio_chip_init()
1139 	gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);  in omap_gpio_chip_init()
1141 	ret = devm_request_irq(bank->dev, bank->irq, omap_gpio_irq_handler,  in omap_gpio_chip_init()
1142 			       0, dev_name(bank->dev), bank);  in omap_gpio_chip_init()
1144 		gpiochip_remove(&bank->chip);  in omap_gpio_chip_init()
1158 	struct gpio_bank *bank;  in omap_gpio_probe()  local
1168 	bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);  in omap_gpio_probe()
1169 	if (!bank) {  in omap_gpio_probe()
1189 	bank->irq = platform_get_irq(pdev, 0);  in omap_gpio_probe()
1190 	if (bank->irq <= 0) {  in omap_gpio_probe()
1191 		if (!bank->irq)  in omap_gpio_probe()
1192 			bank->irq = -ENXIO;  in omap_gpio_probe()
1193 		if (bank->irq != -EPROBE_DEFER)  in omap_gpio_probe()
1195 				"can't get irq resource ret=%d\n", bank->irq);  in omap_gpio_probe()
1196 		return bank->irq;  in omap_gpio_probe()
1199 	bank->dev = dev;  in omap_gpio_probe()
1200 	bank->chip.dev = dev;  in omap_gpio_probe()
1201 	bank->chip.owner = THIS_MODULE;  in omap_gpio_probe()
1202 	bank->dbck_flag = pdata->dbck_flag;  in omap_gpio_probe()
1203 	bank->stride = pdata->bank_stride;  in omap_gpio_probe()
1204 	bank->width = pdata->bank_width;  in omap_gpio_probe()
1205 	bank->is_mpuio = pdata->is_mpuio;  in omap_gpio_probe()
1206 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;  in omap_gpio_probe()
1207 	bank->regs = pdata->regs;  in omap_gpio_probe()
1209 	bank->chip.of_node = of_node_get(node);  in omap_gpio_probe()
1213 			bank->loses_context = true;  in omap_gpio_probe()
1215 		bank->loses_context = pdata->loses_context;  in omap_gpio_probe()
1217 		if (bank->loses_context)  in omap_gpio_probe()
1218 			bank->get_context_loss_count =  in omap_gpio_probe()
1222 	if (bank->regs->set_dataout && bank->regs->clr_dataout)  in omap_gpio_probe()
1223 		bank->set_dataout = omap_set_gpio_dataout_reg;  in omap_gpio_probe()
1225 		bank->set_dataout = omap_set_gpio_dataout_mask;  in omap_gpio_probe()
1227 	raw_spin_lock_init(&bank->lock);  in omap_gpio_probe()
1228 	raw_spin_lock_init(&bank->wa_lock);  in omap_gpio_probe()
1232 	bank->base = devm_ioremap_resource(dev, res);  in omap_gpio_probe()
1233 	if (IS_ERR(bank->base)) {  in omap_gpio_probe()
1234 		return PTR_ERR(bank->base);  in omap_gpio_probe()
1237 	if (bank->dbck_flag) {  in omap_gpio_probe()
1238 		bank->dbck = devm_clk_get(bank->dev, "dbclk");  in omap_gpio_probe()
1239 		if (IS_ERR(bank->dbck)) {  in omap_gpio_probe()
1240 			dev_err(bank->dev,  in omap_gpio_probe()
1242 			bank->dbck_flag = false;  in omap_gpio_probe()
1244 			clk_prepare(bank->dbck);  in omap_gpio_probe()
1248 	platform_set_drvdata(pdev, bank);  in omap_gpio_probe()
1250 	pm_runtime_enable(bank->dev);  in omap_gpio_probe()
1251 	pm_runtime_irq_safe(bank->dev);  in omap_gpio_probe()
1252 	pm_runtime_get_sync(bank->dev);  in omap_gpio_probe()
1254 	if (bank->is_mpuio)  in omap_gpio_probe()
1255 		omap_mpuio_init(bank);  in omap_gpio_probe()
1257 	omap_gpio_mod_init(bank);  in omap_gpio_probe()
1259 	ret = omap_gpio_chip_init(bank, irqc);  in omap_gpio_probe()
1261 		pm_runtime_put_sync(bank->dev);  in omap_gpio_probe()
1262 		pm_runtime_disable(bank->dev);  in omap_gpio_probe()
1266 	omap_gpio_show_rev(bank);  in omap_gpio_probe()
1268 	pm_runtime_put(bank->dev);  in omap_gpio_probe()
1270 	list_add_tail(&bank->node, &omap_gpio_list);  in omap_gpio_probe()
1277 	struct gpio_bank *bank = platform_get_drvdata(pdev);  in omap_gpio_remove()  local
1279 	list_del(&bank->node);  in omap_gpio_remove()
1280 	gpiochip_remove(&bank->chip);  in omap_gpio_remove()
1281 	pm_runtime_disable(bank->dev);  in omap_gpio_remove()
1282 	if (bank->dbck_flag)  in omap_gpio_remove()
1283 		clk_unprepare(bank->dbck);  in omap_gpio_remove()
1291 static void omap_gpio_restore_context(struct gpio_bank *bank);
1296 	struct gpio_bank *bank = platform_get_drvdata(pdev);  in omap_gpio_runtime_suspend()  local
1301 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_runtime_suspend()
1314 	wake_low = bank->context.leveldetect0 & bank->context.wake_en;  in omap_gpio_runtime_suspend()
1316 		writel_relaxed(wake_low | bank->context.fallingdetect,  in omap_gpio_runtime_suspend()
1317 			     bank->base + bank->regs->fallingdetect);  in omap_gpio_runtime_suspend()
1318 	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;  in omap_gpio_runtime_suspend()
1320 		writel_relaxed(wake_hi | bank->context.risingdetect,  in omap_gpio_runtime_suspend()
1321 			     bank->base + bank->regs->risingdetect);  in omap_gpio_runtime_suspend()
1323 	if (!bank->enabled_non_wakeup_gpios)  in omap_gpio_runtime_suspend()
1326 	if (bank->power_mode != OFF_MODE) {  in omap_gpio_runtime_suspend()
1327 		bank->power_mode = 0;  in omap_gpio_runtime_suspend()
1335 	bank->saved_datain = readl_relaxed(bank->base +  in omap_gpio_runtime_suspend()
1336 						bank->regs->datain);  in omap_gpio_runtime_suspend()
1337 	l1 = bank->context.fallingdetect;  in omap_gpio_runtime_suspend()
1338 	l2 = bank->context.risingdetect;  in omap_gpio_runtime_suspend()
1340 	l1 &= ~bank->enabled_non_wakeup_gpios;  in omap_gpio_runtime_suspend()
1341 	l2 &= ~bank->enabled_non_wakeup_gpios;  in omap_gpio_runtime_suspend()
1343 	writel_relaxed(l1, bank->base + bank->regs->fallingdetect);  in omap_gpio_runtime_suspend()
1344 	writel_relaxed(l2, bank->base + bank->regs->risingdetect);  in omap_gpio_runtime_suspend()
1346 	bank->workaround_enabled = true;  in omap_gpio_runtime_suspend()
1349 	if (bank->get_context_loss_count)  in omap_gpio_runtime_suspend()
1350 		bank->context_loss_count =  in omap_gpio_runtime_suspend()
1351 				bank->get_context_loss_count(bank->dev);  in omap_gpio_runtime_suspend()
1353 	omap_gpio_dbck_disable(bank);  in omap_gpio_runtime_suspend()
1354 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_suspend()
1364 	struct gpio_bank *bank = platform_get_drvdata(pdev);  in omap_gpio_runtime_resume()  local
1369 	raw_spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_runtime_resume()
1376 	if (bank->loses_context && !bank->context_valid) {  in omap_gpio_runtime_resume()
1377 		omap_gpio_init_context(bank);  in omap_gpio_runtime_resume()
1379 		if (bank->get_context_loss_count)  in omap_gpio_runtime_resume()
1380 			bank->context_loss_count =  in omap_gpio_runtime_resume()
1381 				bank->get_context_loss_count(bank->dev);  in omap_gpio_runtime_resume()
1384 	omap_gpio_dbck_enable(bank);  in omap_gpio_runtime_resume()
1392 	writel_relaxed(bank->context.fallingdetect,  in omap_gpio_runtime_resume()
1393 		     bank->base + bank->regs->fallingdetect);  in omap_gpio_runtime_resume()
1394 	writel_relaxed(bank->context.risingdetect,  in omap_gpio_runtime_resume()
1395 		     bank->base + bank->regs->risingdetect);  in omap_gpio_runtime_resume()
1397 	if (bank->loses_context) {  in omap_gpio_runtime_resume()
1398 		if (!bank->get_context_loss_count) {  in omap_gpio_runtime_resume()
1399 			omap_gpio_restore_context(bank);  in omap_gpio_runtime_resume()
1401 			c = bank->get_context_loss_count(bank->dev);  in omap_gpio_runtime_resume()
1402 			if (c != bank->context_loss_count) {  in omap_gpio_runtime_resume()
1403 				omap_gpio_restore_context(bank);  in omap_gpio_runtime_resume()
1405 				raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_resume()
1411 	if (!bank->workaround_enabled) {  in omap_gpio_runtime_resume()
1412 		raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_resume()
1416 	l = readl_relaxed(bank->base + bank->regs->datain);  in omap_gpio_runtime_resume()
1424 	l ^= bank->saved_datain;  in omap_gpio_runtime_resume()
1425 	l &= bank->enabled_non_wakeup_gpios;  in omap_gpio_runtime_resume()
1431 	gen0 = l & bank->context.fallingdetect;  in omap_gpio_runtime_resume()
1432 	gen0 &= bank->saved_datain;  in omap_gpio_runtime_resume()
1434 	gen1 = l & bank->context.risingdetect;  in omap_gpio_runtime_resume()
1435 	gen1 &= ~(bank->saved_datain);  in omap_gpio_runtime_resume()
1438 	gen = l & (~(bank->context.fallingdetect) &  in omap_gpio_runtime_resume()
1439 					 ~(bank->context.risingdetect));  in omap_gpio_runtime_resume()
1446 		old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1447 		old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1449 		if (!bank->regs->irqstatus_raw0) {  in omap_gpio_runtime_resume()
1450 			writel_relaxed(old0 | gen, bank->base +  in omap_gpio_runtime_resume()
1451 						bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1452 			writel_relaxed(old1 | gen, bank->base +  in omap_gpio_runtime_resume()
1453 						bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1456 		if (bank->regs->irqstatus_raw0) {  in omap_gpio_runtime_resume()
1457 			writel_relaxed(old0 | l, bank->base +  in omap_gpio_runtime_resume()
1458 						bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1459 			writel_relaxed(old1 | l, bank->base +  in omap_gpio_runtime_resume()
1460 						bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1462 		writel_relaxed(old0, bank->base + bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1463 		writel_relaxed(old1, bank->base + bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1466 	bank->workaround_enabled = false;  in omap_gpio_runtime_resume()
1467 	raw_spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_resume()
1476 	struct gpio_bank *bank;  in omap2_gpio_prepare_for_idle()  local
1478 	list_for_each_entry(bank, &omap_gpio_list, node) {  in omap2_gpio_prepare_for_idle()
1479 		if (!BANK_USED(bank) || !bank->loses_context)  in omap2_gpio_prepare_for_idle()
1482 		bank->power_mode = pwr_mode;  in omap2_gpio_prepare_for_idle()
1484 		pm_runtime_put_sync_suspend(bank->dev);  in omap2_gpio_prepare_for_idle()
1490 	struct gpio_bank *bank;  in omap2_gpio_resume_after_idle()  local
1492 	list_for_each_entry(bank, &omap_gpio_list, node) {  in omap2_gpio_resume_after_idle()
1493 		if (!BANK_USED(bank) || !bank->loses_context)  in omap2_gpio_resume_after_idle()
1496 		pm_runtime_get_sync(bank->dev);  in omap2_gpio_resume_after_idle()
1525 static void omap_gpio_restore_context(struct gpio_bank *bank)  in omap_gpio_restore_context()  argument
1527 	writel_relaxed(bank->context.wake_en,  in omap_gpio_restore_context()
1528 				bank->base + bank->regs->wkup_en);  in omap_gpio_restore_context()
1529 	writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);  in omap_gpio_restore_context()
1530 	writel_relaxed(bank->context.leveldetect0,  in omap_gpio_restore_context()
1531 				bank->base + bank->regs->leveldetect0);  in omap_gpio_restore_context()
1532 	writel_relaxed(bank->context.leveldetect1,  in omap_gpio_restore_context()
1533 				bank->base + bank->regs->leveldetect1);  in omap_gpio_restore_context()
1534 	writel_relaxed(bank->context.risingdetect,  in omap_gpio_restore_context()
1535 				bank->base + bank->regs->risingdetect);  in omap_gpio_restore_context()
1536 	writel_relaxed(bank->context.fallingdetect,  in omap_gpio_restore_context()
1537 				bank->base + bank->regs->fallingdetect);  in omap_gpio_restore_context()
1538 	if (bank->regs->set_dataout && bank->regs->clr_dataout)  in omap_gpio_restore_context()
1539 		writel_relaxed(bank->context.dataout,  in omap_gpio_restore_context()
1540 				bank->base + bank->regs->set_dataout);  in omap_gpio_restore_context()
1542 		writel_relaxed(bank->context.dataout,  in omap_gpio_restore_context()
1543 				bank->base + bank->regs->dataout);  in omap_gpio_restore_context()
1544 	writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);  in omap_gpio_restore_context()
1546 	if (bank->dbck_enable_mask) {  in omap_gpio_restore_context()
1547 		writel_relaxed(bank->context.debounce, bank->base +  in omap_gpio_restore_context()
1548 					bank->regs->debounce);  in omap_gpio_restore_context()
1549 		writel_relaxed(bank->context.debounce_en,  in omap_gpio_restore_context()
1550 					bank->base + bank->regs->debounce_en);  in omap_gpio_restore_context()
1553 	writel_relaxed(bank->context.irqenable1,  in omap_gpio_restore_context()
1554 				bank->base + bank->regs->irqenable);  in omap_gpio_restore_context()
1555 	writel_relaxed(bank->context.irqenable2,  in omap_gpio_restore_context()
1556 				bank->base + bank->regs->irqenable2);  in omap_gpio_restore_context()