276 	list_for_each_entry(bo_va, &bo->va, bo_list) {  in amdgpu_vm_bo_find()
976 	list_add_tail(&bo_va->bo_list, &bo->va);  in amdgpu_vm_bo_add()
1028 	it = interval_tree_iter_first(&vm->va, saddr, eaddr);  in amdgpu_vm_bo_map()
1057 	interval_tree_insert(&mapping->it, &vm->va);  in amdgpu_vm_bo_map()
1106 	interval_tree_remove(&mapping->it, &vm->va);  in amdgpu_vm_bo_map()
1158 	interval_tree_remove(&mapping->it, &vm->va);  in amdgpu_vm_bo_unmap()
1198 		interval_tree_remove(&mapping->it, &vm->va);  in amdgpu_vm_bo_rmv()
1208 		interval_tree_remove(&mapping->it, &vm->va);  in amdgpu_vm_bo_rmv()
1231 	list_for_each_entry(bo_va, &bo->va, bo_list) {  in amdgpu_vm_bo_invalidate()
1258 	vm->va = RB_ROOT;  in amdgpu_vm_init()
1314 	if (!RB_EMPTY_ROOT(&vm->va)) {  in amdgpu_vm_fini()
1317 	rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {  in amdgpu_vm_fini()
1319 		interval_tree_remove(&mapping->it, &vm->va);  in amdgpu_vm_fini()