45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =  variable
173 	return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;  in cik_sdma_ring_get_wptr()
188 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);  in cik_sdma_ring_set_wptr()
340 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in cik_sdma_gfx_stop()
342 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_stop()
343 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_stop()
380 		me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);  in cik_sdma_enable()
385 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);  in cik_sdma_enable()
413 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
414 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
420 		WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
421 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
430 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_resume()
433 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
434 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
437 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],  in cik_sdma_gfx_resume()
439 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],  in cik_sdma_gfx_resume()
444 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);  in cik_sdma_gfx_resume()
445 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);  in cik_sdma_gfx_resume()
448 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);  in cik_sdma_gfx_resume()
451 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],  in cik_sdma_gfx_resume()
459 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in cik_sdma_gfx_resume()
520 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);  in cik_sdma_load_microcode()
522 			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
523 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);  in cik_sdma_load_microcode()
1075 			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));  in cik_sdma_print_status()
1077 			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1079 			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1081 			 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1083 			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1085 			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1087 			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1089 			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));  in cik_sdma_print_status()
1091 			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));  in cik_sdma_print_status()
1093 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));  in cik_sdma_print_status()
1095 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));  in cik_sdma_print_status()
1097 			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));  in cik_sdma_print_status()
1099 			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));  in cik_sdma_print_status()
1105 				 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));  in cik_sdma_print_status()
1107 				 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()