Lines Matching refs:ih
67 adev->irq.ih.enabled = true; in cz_ih_enable_interrupts()
89 adev->irq.ih.enabled = false; in cz_ih_disable_interrupts()
90 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cz_ih_irq_init()
128 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
137 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in cz_ih_irq_init()
193 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cz_ih_get_wptr()
202 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
203 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cz_ih_get_wptr()
208 return (wptr & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
223 u32 ring_index = adev->irq.ih.rptr >> 2; in cz_ih_decode_iv()
226 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); in cz_ih_decode_iv()
227 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); in cz_ih_decode_iv()
228 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); in cz_ih_decode_iv()
229 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); in cz_ih_decode_iv()
238 adev->irq.ih.rptr += 16; in cz_ih_decode_iv()
250 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); in cz_ih_set_rptr()