1432 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_afmt_audio_select_pin()
1435 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_audio_select_pin()
1436 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);  in dce_v10_0_afmt_audio_select_pin()
1437 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_audio_select_pin()
1451 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_latency_fields()
1479 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_latency_fields()
1494 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_speaker_allocation()
1516 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1529 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1560 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_sad_regs()
1611 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);  in dce_v10_0_audio_write_sad_regs()
1692 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1694 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1695 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1697 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1699 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1701 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1702 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1704 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1706 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1708 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1709 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1711 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1728 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1730 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1732 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1734 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1749 	if (!dig || !dig->afmt)  in dce_v10_0_audio_set_dto()
1782 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_setmode()
1786 	if (!dig->afmt->enabled)  in dce_v10_0_afmt_setmode()
1796 	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);  in dce_v10_0_afmt_setmode()
1797 	dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_setmode()
1801 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1803 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */  in dce_v10_0_afmt_setmode()
1805 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);  in dce_v10_0_afmt_setmode()
1807 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1832 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1834 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1838 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1840 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1845 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1847 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1850 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1852 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1855 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1857 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */  in dce_v10_0_afmt_setmode()
1859 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1864 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1866 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1869 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1871 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1880 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1884 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1886 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1888 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1890 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1892 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1899 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1903 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,  in dce_v10_0_afmt_setmode()
1924 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1929 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1931 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1933 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1935 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1938 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1940 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);  in dce_v10_0_afmt_setmode()
1941 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);  in dce_v10_0_afmt_setmode()
1942 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1943 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1946 	dce_v10_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v10_0_afmt_setmode()
1956 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_enable()
1960 	if (enable && dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1962 	if (!enable && !dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1965 	if (!enable && dig->afmt->pin) {  in dce_v10_0_afmt_enable()
1966 		dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_enable()
1967 		dig->afmt->pin = NULL;  in dce_v10_0_afmt_enable()
1970 	dig->afmt->enabled = enable;  in dce_v10_0_afmt_enable()
1973 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);  in dce_v10_0_afmt_enable()
1981 		adev->mode_info.afmt[i] = NULL;  in dce_v10_0_afmt_init()
1985 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);  in dce_v10_0_afmt_init()
1986 		if (adev->mode_info.afmt[i]) {  in dce_v10_0_afmt_init()
1987 			adev->mode_info.afmt[i]->offset = dig_offsets[i];  in dce_v10_0_afmt_init()
1988 			adev->mode_info.afmt[i]->id = i;  in dce_v10_0_afmt_init()
1998 		kfree(adev->mode_info.afmt[i]);  in dce_v10_0_afmt_fini()
1999 		adev->mode_info.afmt[i] = NULL;  in dce_v10_0_afmt_fini()
3546 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v10_0_encoder_prepare()