Lines Matching refs:crtc
192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) in dce_v10_0_is_in_vblank() argument
194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v10_0_is_in_vblank()
201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) in dce_v10_0_is_counter_moving() argument
205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_is_counter_moving()
206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_is_counter_moving()
222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) in dce_v10_0_vblank_wait() argument
226 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_wait()
229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v10_0_vblank_wait()
235 while (dce_v10_0_is_in_vblank(adev, crtc)) { in dce_v10_0_vblank_wait()
237 if (!dce_v10_0_is_counter_moving(adev, crtc)) in dce_v10_0_vblank_wait()
242 while (!dce_v10_0_is_in_vblank(adev, crtc)) { in dce_v10_0_vblank_wait()
244 if (!dce_v10_0_is_counter_moving(adev, crtc)) in dce_v10_0_vblank_wait()
250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) in dce_v10_0_vblank_get_counter() argument
252 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_get_counter()
255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v10_0_vblank_get_counter()
301 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, in dce_v10_0_crtc_get_scanoutpos() argument
304 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v10_0_crtc_get_scanoutpos()
307 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
308 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
714 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_program_fmt()
1744 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_audio_set_dto()
1790 if (encoder->crtc) { in dce_v10_0_afmt_setmode()
1791 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_afmt_setmode()
2013 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) in dce_v10_0_vga_enable() argument
2015 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_vga_enable()
2016 struct drm_device *dev = crtc->dev; in dce_v10_0_vga_enable()
2027 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) in dce_v10_0_grph_enable() argument
2029 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_grph_enable()
2030 struct drm_device *dev = crtc->dev; in dce_v10_0_grph_enable()
2039 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, in dce_v10_0_crtc_do_set_base() argument
2043 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_do_set_base()
2044 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_do_set_base()
2059 if (!atomic && !crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
2069 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); in dce_v10_0_crtc_do_set_base()
2070 target_fb = crtc->primary->fb; in dce_v10_0_crtc_do_set_base()
2202 dce_v10_0_vga_enable(crtc, false); in dce_v10_0_crtc_do_set_base()
2240 dce_v10_0_grph_enable(crtc, true); in dce_v10_0_crtc_do_set_base()
2249 viewport_w = crtc->mode.hdisplay; in dce_v10_0_crtc_do_set_base()
2250 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v10_0_crtc_do_set_base()
2264 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
2280 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, in dce_v10_0_set_interleave() argument
2283 struct drm_device *dev = crtc->dev; in dce_v10_0_set_interleave()
2285 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_set_interleave()
2296 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) in dce_v10_0_crtc_load_lut() argument
2298 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_load_lut()
2299 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_load_lut()
2431 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) in dce_v10_0_pick_pll() argument
2433 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_pick_pll()
2434 struct drm_device *dev = crtc->dev; in dce_v10_0_pick_pll()
2445 pll = amdgpu_pll_get_shared_dp_ppll(crtc); in dce_v10_0_pick_pll()
2451 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); in dce_v10_0_pick_pll()
2457 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v10_0_pick_pll()
2468 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) in dce_v10_0_lock_cursor() argument
2470 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_lock_cursor()
2471 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_lock_cursor()
2482 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) in dce_v10_0_hide_cursor() argument
2484 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_hide_cursor()
2485 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_hide_cursor()
2493 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) in dce_v10_0_show_cursor() argument
2495 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_show_cursor()
2496 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_show_cursor()
2510 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, in dce_v10_0_cursor_move_locked() argument
2513 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_cursor_move_locked()
2514 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_cursor_move_locked()
2518 x += crtc->x; in dce_v10_0_cursor_move_locked()
2519 y += crtc->y; in dce_v10_0_cursor_move_locked()
2520 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v10_0_cursor_move_locked()
2542 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, in dce_v10_0_crtc_cursor_move() argument
2547 dce_v10_0_lock_cursor(crtc, true); in dce_v10_0_crtc_cursor_move()
2548 ret = dce_v10_0_cursor_move_locked(crtc, x, y); in dce_v10_0_crtc_cursor_move()
2549 dce_v10_0_lock_cursor(crtc, false); in dce_v10_0_crtc_cursor_move()
2554 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, in dce_v10_0_crtc_cursor_set2() argument
2562 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_cursor_set2()
2569 dce_v10_0_hide_cursor(crtc); in dce_v10_0_crtc_cursor_set2()
2580 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); in dce_v10_0_crtc_cursor_set2()
2604 dce_v10_0_lock_cursor(crtc, true); in dce_v10_0_crtc_cursor_set2()
2613 dce_v10_0_cursor_move_locked(crtc, x, y); in dce_v10_0_crtc_cursor_set2()
2619 dce_v10_0_show_cursor(crtc); in dce_v10_0_crtc_cursor_set2()
2620 dce_v10_0_lock_cursor(crtc, false); in dce_v10_0_crtc_cursor_set2()
2637 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) in dce_v10_0_cursor_reset() argument
2639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_cursor_reset()
2642 dce_v10_0_lock_cursor(crtc, true); in dce_v10_0_cursor_reset()
2644 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v10_0_cursor_reset()
2647 dce_v10_0_show_cursor(crtc); in dce_v10_0_cursor_reset()
2649 dce_v10_0_lock_cursor(crtc, false); in dce_v10_0_cursor_reset()
2653 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, in dce_v10_0_crtc_gamma_set() argument
2656 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_gamma_set()
2665 dce_v10_0_crtc_load_lut(crtc); in dce_v10_0_crtc_gamma_set()
2668 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) in dce_v10_0_crtc_destroy() argument
2670 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_destroy()
2672 drm_crtc_cleanup(crtc); in dce_v10_0_crtc_destroy()
2686 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) in dce_v10_0_crtc_dpms() argument
2688 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_dpms()
2690 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_dpms()
2696 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); in dce_v10_0_crtc_dpms()
2697 dce_v10_0_vga_enable(crtc, true); in dce_v10_0_crtc_dpms()
2698 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); in dce_v10_0_crtc_dpms()
2699 dce_v10_0_vga_enable(crtc, false); in dce_v10_0_crtc_dpms()
2705 dce_v10_0_crtc_load_lut(crtc); in dce_v10_0_crtc_dpms()
2712 dce_v10_0_vga_enable(crtc, true); in dce_v10_0_crtc_dpms()
2713 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); in dce_v10_0_crtc_dpms()
2714 dce_v10_0_vga_enable(crtc, false); in dce_v10_0_crtc_dpms()
2716 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); in dce_v10_0_crtc_dpms()
2724 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) in dce_v10_0_crtc_prepare() argument
2727 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); in dce_v10_0_crtc_prepare()
2728 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); in dce_v10_0_crtc_prepare()
2729 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); in dce_v10_0_crtc_prepare()
2732 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) in dce_v10_0_crtc_commit() argument
2734 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); in dce_v10_0_crtc_commit()
2735 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); in dce_v10_0_crtc_commit()
2738 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) in dce_v10_0_crtc_disable() argument
2740 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_disable()
2741 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_disable()
2746 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); in dce_v10_0_crtc_disable()
2747 if (crtc->primary->fb) { in dce_v10_0_crtc_disable()
2752 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); in dce_v10_0_crtc_disable()
2763 dce_v10_0_grph_enable(crtc, false); in dce_v10_0_crtc_disable()
2765 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); in dce_v10_0_crtc_disable()
2784 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v10_0_crtc_disable()
2797 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, in dce_v10_0_crtc_mode_set() argument
2802 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_mode_set()
2807 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); in dce_v10_0_crtc_mode_set()
2808 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); in dce_v10_0_crtc_mode_set()
2809 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); in dce_v10_0_crtc_mode_set()
2810 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); in dce_v10_0_crtc_mode_set()
2811 amdgpu_atombios_crtc_scaler_setup(crtc); in dce_v10_0_crtc_mode_set()
2812 dce_v10_0_cursor_reset(crtc); in dce_v10_0_crtc_mode_set()
2819 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, in dce_v10_0_crtc_mode_fixup() argument
2823 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_mode_fixup()
2824 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_mode_fixup()
2829 if (encoder->crtc == crtc) { in dce_v10_0_crtc_mode_fixup()
2840 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) in dce_v10_0_crtc_mode_fixup()
2842 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) in dce_v10_0_crtc_mode_fixup()
2845 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); in dce_v10_0_crtc_mode_fixup()
2854 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, in dce_v10_0_crtc_set_base() argument
2857 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); in dce_v10_0_crtc_set_base()
2860 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, in dce_v10_0_crtc_set_base_atomic() argument
2864 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); in dce_v10_0_crtc_set_base_atomic()
3163 int crtc, in dce_v10_0_set_crtc_vblank_interrupt_state() argument
3168 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vblank_interrupt_state()
3169 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_set_crtc_vblank_interrupt_state()
3175 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3178 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3181 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3184 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3192 int crtc, in dce_v10_0_set_crtc_vline_interrupt_state() argument
3197 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vline_interrupt_state()
3198 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_set_crtc_vline_interrupt_state()
3204 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3207 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vline_interrupt_state()
3210 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3213 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vline_interrupt_state()
3390 int crtc) in dce_v10_0_crtc_vblank_int_ack() argument
3394 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vblank_int_ack()
3395 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_crtc_vblank_int_ack()
3399 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vblank_int_ack()
3401 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vblank_int_ack()
3405 int crtc) in dce_v10_0_crtc_vline_int_ack() argument
3409 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vline_int_ack()
3410 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_crtc_vline_int_ack()
3414 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vline_int_ack()
3416 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vline_int_ack()
3423 unsigned crtc = entry->src_id - 1; in dce_v10_0_crtc_irq() local
3424 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()
3425 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); in dce_v10_0_crtc_irq()
3429 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3430 dce_v10_0_crtc_vblank_int_ack(adev, crtc); in dce_v10_0_crtc_irq()
3435 drm_handle_vblank(adev->ddev, crtc); in dce_v10_0_crtc_irq()
3437 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); in dce_v10_0_crtc_irq()
3441 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3442 dce_v10_0_crtc_vline_int_ack(adev, crtc); in dce_v10_0_crtc_irq()
3446 DRM_DEBUG("IH: D%d vline\n", crtc + 1); in dce_v10_0_crtc_irq()
3524 dce_v10_0_set_interleave(encoder->crtc, mode); in dce_v10_0_encoder_mode_set()