81 	uint32_t        hpd;  member
87 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
92 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
97 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
102 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
107 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
112 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
323 			       enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_sense()  argument
328 	switch (hpd) {  in dce_v10_0_hpd_sense()
367 				      enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_set_polarity()  argument
370 	bool connected = dce_v10_0_hpd_sense(adev, hpd);  in dce_v10_0_hpd_set_polarity()
373 	switch (hpd) {  in dce_v10_0_hpd_set_polarity()
432 		switch (amdgpu_connector->hpd.hpd) {  in dce_v10_0_hpd_init()
468 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
470 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
492 		switch (amdgpu_connector->hpd.hpd) {  in dce_v10_0_hpd_fini()
520 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_fini()
3222 				       unsigned hpd,  in dce_v10_0_set_hpd_irq_state()  argument
3227 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_set_hpd_irq_state()
3228 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_set_hpd_irq_state()
3234 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3236 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3239 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3241 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3375 				  int hpd)  in dce_v10_0_hpd_int_ack()  argument
3379 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_hpd_int_ack()
3380 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_hpd_int_ack()
3384 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_int_ack()
3386 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_int_ack()
3462 	unsigned hpd;  in dce_v10_0_hpd_irq()  local
3469 	hpd = entry->src_data;  in dce_v10_0_hpd_irq()
3470 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v10_0_hpd_irq()
3471 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v10_0_hpd_irq()
3474 		dce_v10_0_hpd_int_ack(adev, hpd);  in dce_v10_0_hpd_irq()
3476 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v10_0_hpd_irq()