83 	uint32_t        hpd;  member
89 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
94 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
99 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
313 			       enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_sense()  argument
318 	switch (hpd) {  in dce_v11_0_hpd_sense()
357 				      enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_set_polarity()  argument
360 	bool connected = dce_v11_0_hpd_sense(adev, hpd);  in dce_v11_0_hpd_set_polarity()
363 	switch (hpd) {  in dce_v11_0_hpd_set_polarity()
422 		switch (amdgpu_connector->hpd.hpd) {  in dce_v11_0_hpd_init()
458 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
459 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
481 		switch (amdgpu_connector->hpd.hpd) {  in dce_v11_0_hpd_fini()
508 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_fini()
3215 					unsigned hpd,  in dce_v11_0_set_hpd_irq_state()  argument
3220 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_set_hpd_irq_state()
3221 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_set_hpd_irq_state()
3227 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3229 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3232 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3234 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3368 				  int hpd)  in dce_v11_0_hpd_int_ack()  argument
3372 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_int_ack()
3373 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_hpd_int_ack()
3377 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_int_ack()
3379 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_int_ack()
3455 	unsigned hpd;  in dce_v11_0_hpd_irq()  local
3462 	hpd = entry->src_data;  in dce_v11_0_hpd_irq()
3463 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v11_0_hpd_irq()
3464 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v11_0_hpd_irq()
3467 		dce_v11_0_hpd_int_ack(adev, hpd);  in dce_v11_0_hpd_irq()
3469 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v11_0_hpd_irq()