Lines Matching refs:hpd
73 uint32_t hpd; member
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
272 enum amdgpu_hpd_id hpd) in dce_v8_0_hpd_sense() argument
276 switch (hpd) { in dce_v8_0_hpd_sense()
317 enum amdgpu_hpd_id hpd) in dce_v8_0_hpd_set_polarity() argument
320 bool connected = dce_v8_0_hpd_sense(adev, hpd); in dce_v8_0_hpd_set_polarity()
322 switch (hpd) { in dce_v8_0_hpd_set_polarity()
404 switch (amdgpu_connector->hpd.hpd) { in dce_v8_0_hpd_init()
426 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v8_0_hpd_init()
427 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v8_0_hpd_init()
447 switch (amdgpu_connector->hpd.hpd) { in dce_v8_0_hpd_fini()
469 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v8_0_hpd_fini()
3388 unsigned hpd; in dce_v8_0_hpd_irq() local
3395 hpd = entry->src_data; in dce_v8_0_hpd_irq()
3396 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()
3397 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
3398 int_control = hpd_int_control_offsets[hpd]; in dce_v8_0_hpd_irq()
3405 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v8_0_hpd_irq()