3331 	struct bonaire_mqd *mqd;  in gfx_v7_0_cp_compute_resume()  local
3406 		mqd = (struct bonaire_mqd *)buf;  in gfx_v7_0_cp_compute_resume()
3407 		mqd->header = 0xC0310800;  in gfx_v7_0_cp_compute_resume()
3408 		mqd->static_thread_mgmt01[0] = 0xffffffff;  in gfx_v7_0_cp_compute_resume()
3409 		mqd->static_thread_mgmt01[1] = 0xffffffff;  in gfx_v7_0_cp_compute_resume()
3410 		mqd->static_thread_mgmt23[0] = 0xffffffff;  in gfx_v7_0_cp_compute_resume()
3411 		mqd->static_thread_mgmt23[1] = 0xffffffff;  in gfx_v7_0_cp_compute_resume()
3424 		mqd->queue_state.cp_hqd_pq_doorbell_control =  in gfx_v7_0_cp_compute_resume()
3427 			mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;  in gfx_v7_0_cp_compute_resume()
3429 			mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;  in gfx_v7_0_cp_compute_resume()
3431 		       mqd->queue_state.cp_hqd_pq_doorbell_control);  in gfx_v7_0_cp_compute_resume()
3434 		mqd->queue_state.cp_hqd_dequeue_request = 0;  in gfx_v7_0_cp_compute_resume()
3435 		mqd->queue_state.cp_hqd_pq_rptr = 0;  in gfx_v7_0_cp_compute_resume()
3436 		mqd->queue_state.cp_hqd_pq_wptr= 0;  in gfx_v7_0_cp_compute_resume()
3444 			WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);  in gfx_v7_0_cp_compute_resume()
3445 			WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);  in gfx_v7_0_cp_compute_resume()
3446 			WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);  in gfx_v7_0_cp_compute_resume()
3450 		mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;  in gfx_v7_0_cp_compute_resume()
3451 		mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);  in gfx_v7_0_cp_compute_resume()
3452 		WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);  in gfx_v7_0_cp_compute_resume()
3453 		WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);  in gfx_v7_0_cp_compute_resume()
3455 		mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);  in gfx_v7_0_cp_compute_resume()
3456 		mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;  in gfx_v7_0_cp_compute_resume()
3457 		WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);  in gfx_v7_0_cp_compute_resume()
3461 		mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;  in gfx_v7_0_cp_compute_resume()
3462 		mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in gfx_v7_0_cp_compute_resume()
3463 		WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);  in gfx_v7_0_cp_compute_resume()
3464 		WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);  in gfx_v7_0_cp_compute_resume()
3467 		mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);  in gfx_v7_0_cp_compute_resume()
3468 		mqd->queue_state.cp_hqd_pq_control &=  in gfx_v7_0_cp_compute_resume()
3472 		mqd->queue_state.cp_hqd_pq_control |=  in gfx_v7_0_cp_compute_resume()
3474 		mqd->queue_state.cp_hqd_pq_control |=  in gfx_v7_0_cp_compute_resume()
3477 		mqd->queue_state.cp_hqd_pq_control |=  in gfx_v7_0_cp_compute_resume()
3480 		mqd->queue_state.cp_hqd_pq_control &=  in gfx_v7_0_cp_compute_resume()
3484 		mqd->queue_state.cp_hqd_pq_control |=  in gfx_v7_0_cp_compute_resume()
3487 		WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);  in gfx_v7_0_cp_compute_resume()
3491 		mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;  in gfx_v7_0_cp_compute_resume()
3492 		mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v7_0_cp_compute_resume()
3493 		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);  in gfx_v7_0_cp_compute_resume()
3495 		       mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);  in gfx_v7_0_cp_compute_resume()
3499 		mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;  in gfx_v7_0_cp_compute_resume()
3500 		mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =  in gfx_v7_0_cp_compute_resume()
3503 		       mqd->queue_state.cp_hqd_pq_rptr_report_addr);  in gfx_v7_0_cp_compute_resume()
3505 		       mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);  in gfx_v7_0_cp_compute_resume()
3509 			mqd->queue_state.cp_hqd_pq_doorbell_control =  in gfx_v7_0_cp_compute_resume()
3511 			mqd->queue_state.cp_hqd_pq_doorbell_control &=  in gfx_v7_0_cp_compute_resume()
3513 			mqd->queue_state.cp_hqd_pq_doorbell_control |=  in gfx_v7_0_cp_compute_resume()
3516 			mqd->queue_state.cp_hqd_pq_doorbell_control |=  in gfx_v7_0_cp_compute_resume()
3518 			mqd->queue_state.cp_hqd_pq_doorbell_control &=  in gfx_v7_0_cp_compute_resume()
3523 			mqd->queue_state.cp_hqd_pq_doorbell_control = 0;  in gfx_v7_0_cp_compute_resume()
3526 		       mqd->queue_state.cp_hqd_pq_doorbell_control);  in gfx_v7_0_cp_compute_resume()
3530 		mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;  in gfx_v7_0_cp_compute_resume()
3531 		WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);  in gfx_v7_0_cp_compute_resume()
3532 		mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);  in gfx_v7_0_cp_compute_resume()
3535 		mqd->queue_state.cp_hqd_vmid = 0;  in gfx_v7_0_cp_compute_resume()
3536 		WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);  in gfx_v7_0_cp_compute_resume()
3539 		mqd->queue_state.cp_hqd_active = 1;  in gfx_v7_0_cp_compute_resume()
3540 		WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);  in gfx_v7_0_cp_compute_resume()