667 	struct amdgpu_ib ib;  in gfx_v8_0_ring_test_ib()  local
680 	memset(&ib, 0, sizeof(ib));  in gfx_v8_0_ring_test_ib()
681 	r = amdgpu_ib_get(ring, NULL, 256, &ib);  in gfx_v8_0_ring_test_ib()
686 	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);  in gfx_v8_0_ring_test_ib()
687 	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));  in gfx_v8_0_ring_test_ib()
688 	ib.ptr[2] = 0xDEADBEEF;  in gfx_v8_0_ring_test_ib()
689 	ib.length_dw = 3;  in gfx_v8_0_ring_test_ib()
691 	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,  in gfx_v8_0_ring_test_ib()
719 	amdgpu_ib_free(adev, &ib);  in gfx_v8_0_ring_test_ib()
4543 				  struct amdgpu_ib *ib)  in gfx_v8_0_ring_emit_ib_gfx()  argument
4545 	bool need_ctx_switch = ring->current_ctx != ib->ctx;  in gfx_v8_0_ring_emit_ib_gfx()
4550 	if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)  in gfx_v8_0_ring_emit_ib_gfx()
4569 	if (ib->flags & AMDGPU_IB_FLAG_CE)  in gfx_v8_0_ring_emit_ib_gfx()
4574 	control |= ib->length_dw |  in gfx_v8_0_ring_emit_ib_gfx()
4575 		(ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);  in gfx_v8_0_ring_emit_ib_gfx()
4582 			  (ib->gpu_addr & 0xFFFFFFFC));  in gfx_v8_0_ring_emit_ib_gfx()
4583 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in gfx_v8_0_ring_emit_ib_gfx()
4588 				  struct amdgpu_ib *ib)  in gfx_v8_0_ring_emit_ib_compute()  argument
4604 	control |= ib->length_dw |  in gfx_v8_0_ring_emit_ib_compute()
4605 			   (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);  in gfx_v8_0_ring_emit_ib_compute()
4612 					  (ib->gpu_addr & 0xFFFFFFFC));  in gfx_v8_0_ring_emit_ib_compute()
4613 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in gfx_v8_0_ring_emit_ib_compute()