113 		WREG32(mmBIF_FB_EN, 0);  in gmc_v7_0_mc_stop()
117 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);  in gmc_v7_0_mc_stop()
131 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v7_0_mc_resume()
135 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v7_0_mc_resume()
230 			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);  in gmc_v7_0_mc_load_microcode()
234 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v7_0_mc_load_microcode()
235 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v7_0_mc_load_microcode()
239 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v7_0_mc_load_microcode()
240 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v7_0_mc_load_microcode()
244 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v7_0_mc_load_microcode()
247 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v7_0_mc_load_microcode()
248 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v7_0_mc_load_microcode()
249 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v7_0_mc_load_microcode()
266 			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);  in gmc_v7_0_mc_load_microcode()
302 		WREG32((0xb05 + j), 0x00000000);  in gmc_v7_0_mc_program()
303 		WREG32((0xb06 + j), 0x00000000);  in gmc_v7_0_mc_program()
304 		WREG32((0xb07 + j), 0x00000000);  in gmc_v7_0_mc_program()
305 		WREG32((0xb08 + j), 0x00000000);  in gmc_v7_0_mc_program()
306 		WREG32((0xb09 + j), 0x00000000);  in gmc_v7_0_mc_program()
308 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v7_0_mc_program()
318 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v7_0_mc_program()
320 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v7_0_mc_program()
322 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v7_0_mc_program()
326 	WREG32(mmMC_VM_FB_LOCATION, tmp);  in gmc_v7_0_mc_program()
328 	WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));  in gmc_v7_0_mc_program()
329 	WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));  in gmc_v7_0_mc_program()
330 	WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in gmc_v7_0_mc_program()
331 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v7_0_mc_program()
332 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v7_0_mc_program()
333 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v7_0_mc_program()
339 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);  in gmc_v7_0_mc_program()
343 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v7_0_mc_program()
346 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v7_0_mc_program()
442 	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);  in gmc_v7_0_gart_flush_gpu_tlb()
445 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v7_0_gart_flush_gpu_tlb()
499 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_set_fault_enable_default()
532 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_enable()
542 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_enable()
545 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v7_0_gart_enable()
550 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v7_0_gart_enable()
552 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);  in gmc_v7_0_gart_enable()
553 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);  in gmc_v7_0_gart_enable()
554 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);  in gmc_v7_0_gart_enable()
555 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v7_0_gart_enable()
557 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v7_0_gart_enable()
562 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_gart_enable()
564 	WREG32(0x575, 0);  in gmc_v7_0_gart_enable()
565 	WREG32(0x576, 0);  in gmc_v7_0_gart_enable()
566 	WREG32(0x577, 0);  in gmc_v7_0_gart_enable()
573 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v7_0_gart_enable()
574 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v7_0_gart_enable()
577 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v7_0_gart_enable()
580 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v7_0_gart_enable()
585 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v7_0_gart_enable()
587 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v7_0_gart_enable()
593 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_gart_enable()
602 		WREG32(mmCHUB_CONTROL, tmp);  in gmc_v7_0_gart_enable()
641 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v7_0_gart_disable()
642 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v7_0_gart_disable()
648 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_disable()
652 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_disable()
653 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v7_0_gart_disable()
796 			WREG32(mc_cg_registers[i], data);  in gmc_v7_0_enable_mc_ls()
813 			WREG32(mc_cg_registers[i], data);  in gmc_v7_0_enable_mc_mgcg()
853 		WREG32(mmHDP_HOST_PATH_CNTL, data);  in gmc_v7_0_enable_hdp_mgcg()
869 		WREG32(mmHDP_MEM_POWER_LS, data);  in gmc_v7_0_enable_hdp_ls()
1255 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1261 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1294 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1298 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1304 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1308 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()