59 	if (ring == &adev->vce.ring[0])  in vce_v2_0_ring_get_rptr()
76 	if (ring == &adev->vce.ring[0])  in vce_v2_0_ring_get_wptr()
93 	if (ring == &adev->vce.ring[0])  in vce_v2_0_ring_set_wptr()
116 	ring = &adev->vce.ring[0];  in vce_v2_0_start()
123 	ring = &adev->vce.ring[1];  in vce_v2_0_start()
189 	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);  in vce_v2_0_sw_init()
202 	ring = &adev->vce.ring[0];  in vce_v2_0_sw_init()
205 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);  in vce_v2_0_sw_init()
209 	ring = &adev->vce.ring[1];  in vce_v2_0_sw_init()
212 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);  in vce_v2_0_sw_init()
245 	ring = &adev->vce.ring[0];  in vce_v2_0_hw_init()
253 	ring = &adev->vce.ring[1];  in vce_v2_0_hw_init()
414 	uint64_t addr = adev->vce.gpu_addr;  in vce_v2_0_mc_resume()
571 		amdgpu_fence_process(&adev->vce.ring[0]);  in vce_v2_0_process_interrupt()
574 		amdgpu_fence_process(&adev->vce.ring[1]);  in vce_v2_0_process_interrupt()
650 	adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;  in vce_v2_0_set_ring_funcs()
651 	adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;  in vce_v2_0_set_ring_funcs()
661 	adev->vce.irq.num_types = 1;  in vce_v2_0_set_irq_funcs()
662 	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;  in vce_v2_0_set_irq_funcs()