Lines Matching refs:vce
66 if (ring == &adev->vce.ring[0]) in vce_v3_0_ring_get_rptr()
83 if (ring == &adev->vce.ring[0]) in vce_v3_0_ring_get_wptr()
100 if (ring == &adev->vce.ring[0]) in vce_v3_0_ring_set_wptr()
121 if (adev->vce.harvest_config & (1 << idx)) in vce_v3_0_start()
187 ring = &adev->vce.ring[0]; in vce_v3_0_start()
194 ring = &adev->vce.ring[1]; in vce_v3_0_start()
251 adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev); in vce_v3_0_early_init()
253 if ((adev->vce.harvest_config & in vce_v3_0_early_init()
271 r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); in vce_v3_0_sw_init()
284 ring = &adev->vce.ring[0]; in vce_v3_0_sw_init()
287 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); in vce_v3_0_sw_init()
291 ring = &adev->vce.ring[1]; in vce_v3_0_sw_init()
294 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); in vce_v3_0_sw_init()
327 ring = &adev->vce.ring[0]; in vce_v3_0_hw_init()
335 ring = &adev->vce.ring[1]; in vce_v3_0_hw_init()
400 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
401 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
402 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
404 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
443 if (adev->vce.harvest_config & (1 << idx)) in vce_v3_0_is_idle()
463 if (adev->vce.harvest_config & (1 << idx)) in vce_v3_0_wait_for_idle()
486 if (adev->vce.harvest_config & (1 << idx)) in vce_v3_0_soft_reset()
595 amdgpu_fence_process(&adev->vce.ring[0]); in vce_v3_0_process_interrupt()
598 amdgpu_fence_process(&adev->vce.ring[1]); in vce_v3_0_process_interrupt()
666 adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs; in vce_v3_0_set_ring_funcs()
667 adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs; in vce_v3_0_set_ring_funcs()
677 adev->vce.irq.num_types = 1; in vce_v3_0_set_irq_funcs()
678 adev->vce.irq.funcs = &vce_v3_0_irq_funcs; in vce_v3_0_set_irq_funcs()