324 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);  in vi_srbm_select()
325 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);  in vi_srbm_select()
326 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);  in vi_srbm_select()
327 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);  in vi_srbm_select()
722 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);  in vi_gpu_soft_reset()
723 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);  in vi_gpu_soft_reset()
724 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);  in vi_gpu_soft_reset()
729 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);  in vi_gpu_soft_reset()
730 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);  in vi_gpu_soft_reset()
736 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_soft_reset()
742 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_soft_reset()
753 			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);  in vi_gpu_soft_reset()
755 			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);  in vi_gpu_soft_reset()
760 			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);  in vi_gpu_soft_reset()
762 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);  in vi_gpu_soft_reset()
767 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);  in vi_gpu_soft_reset()
771 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);  in vi_gpu_soft_reset()
775 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);  in vi_gpu_soft_reset()
779 			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);  in vi_gpu_soft_reset()
783 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);  in vi_gpu_soft_reset()
787 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);  in vi_gpu_soft_reset()
791 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);  in vi_gpu_soft_reset()
795 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);  in vi_gpu_soft_reset()
799 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);  in vi_gpu_soft_reset()
803 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);  in vi_gpu_soft_reset()
807 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);  in vi_gpu_soft_reset()
812 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);  in vi_gpu_soft_reset()
865 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);  in vi_gpu_pci_config_reset()
866 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);  in vi_gpu_pci_config_reset()
867 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);  in vi_gpu_pci_config_reset()
872 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);  in vi_gpu_pci_config_reset()
873 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);  in vi_gpu_pci_config_reset()
886 	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_pci_config_reset()
891 	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_pci_config_reset()
1065 		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);  in vi_enable_doorbell_aperture()
1067 		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);  in vi_enable_doorbell_aperture()