Lines Matching refs:uint32_t
46 uint32_t cpu_cores_count;
47 uint32_t simd_count;
48 uint32_t mem_banks_count;
49 uint32_t caches_count;
50 uint32_t io_links_count;
51 uint32_t cpu_core_id_base;
52 uint32_t simd_id_base;
53 uint32_t capability;
54 uint32_t max_waves_per_simd;
55 uint32_t lds_size_in_kb;
56 uint32_t gds_size_in_kb;
57 uint32_t wave_front_size;
58 uint32_t array_count;
59 uint32_t simd_arrays_per_engine;
60 uint32_t cu_per_simd_array;
61 uint32_t simd_per_cu;
62 uint32_t max_slots_scratch_cu;
63 uint32_t engine_id;
64 uint32_t vendor_id;
65 uint32_t device_id;
66 uint32_t location_id;
67 uint32_t max_engine_clk_fcompute;
68 uint32_t max_engine_clk_ccompute;
85 uint32_t heap_type;
87 uint32_t flags;
88 uint32_t width;
89 uint32_t mem_clk_max;
104 uint32_t processor_id_low;
105 uint32_t cache_level;
106 uint32_t cache_size;
107 uint32_t cacheline_size;
108 uint32_t cachelines_per_tag;
109 uint32_t cache_assoc;
110 uint32_t cache_latency;
111 uint32_t cache_type;
119 uint32_t iolink_type;
120 uint32_t ver_maj;
121 uint32_t ver_min;
122 uint32_t node_from;
123 uint32_t node_to;
124 uint32_t weight;
125 uint32_t min_latency;
126 uint32_t max_latency;
127 uint32_t min_bandwidth;
128 uint32_t max_bandwidth;
129 uint32_t rec_transfer_size;
130 uint32_t flags;
137 uint32_t gpu_id;
139 uint32_t mem_bank_count;
141 uint32_t cache_count;
143 uint32_t io_link_count;
156 uint32_t num_devices; /* Number of H-NUMA nodes */
157 uint32_t generation_count;