Lines Matching refs:ULONG
44 #ifndef ULONG
45 typedef unsigned long ULONG; typedef
384 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
385 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
386 ULONG ulClockFreq:24;
388 ULONG ulClockFreq:24;
389 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
390 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
397 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
406 ULONG ulClock; //When return, [23:0] return real clock
432 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
433 ULONG ulClockFreq:24; // in unit of 10kHz
435 ULONG ulClockFreq:24; // in unit of 10kHz
436 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
470 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
471 ULONG ulClock:24; //Input= target clock, output = actual clock
473 ULONG ulClock:24; //Input= target clock, output = actual clock
474 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
499 ULONG ulReserved[2];
530 ULONG ulClock;
556 ULONG ulReserved[2];
562 ULONG ulMemoryClock;
563 ULONG ulReserved;
571 ULONG ulTargetEngineClock; //In 10Khz unit
576 ULONG ulTargetEngineClock; //In 10Khz unit
585 ULONG ulTargetMemoryClock; //In 10Khz unit
590 ULONG ulTargetMemoryClock; //In 10Khz unit
599 ULONG ulDefaultEngineClock; //In 10Khz unit
600 ULONG ulDefaultMemoryClock; //In 10Khz unit
611 ULONG ulClkFreqIn10Khz:24;
612 ULONG ucClkFlag:8;
624 ULONG ulReserved[8];
652 ULONG ulReserved[4];
681 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
1412 ULONG ulReserved[2];
1698 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1713 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1715 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1718 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1720 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1729 ULONG ulDispEngClkFreq; // dispclk frequency
1746 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1825 …ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pix…
1856 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1865 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2046 ULONG ulTargetMemoryClock; //In 10Khz unit
2338 ULONG ulReserved;
2344 ULONG ulVotlageGpioState;
2345 ULONG ulVoltageGPioMask;
2353 ULONG ulReseved;
2377 …ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, …
2472 ULONG ulSignature; // HW info table signature string "$ATI"
2486 ULONG ulSignature; // MM info table signature sting "$MMT"
2581 ULONG ulFirmwareRevision;
2582 ULONG ulDefaultEngineClock; //In 10Khz unit
2583 ULONG ulDefaultMemoryClock; //In 10Khz unit
2584 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2585 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2586 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2587 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2588 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2589 ULONG ulASICMaxEngineClock; //In 10Khz unit
2590 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2593 ULONG aulReservedForBIOS[3]; //Don't use them
2615 ULONG ulFirmwareRevision;
2616 ULONG ulDefaultEngineClock; //In 10Khz unit
2617 ULONG ulDefaultMemoryClock; //In 10Khz unit
2618 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2619 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2620 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2621 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2622 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2623 ULONG ulASICMaxEngineClock; //In 10Khz unit
2624 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2628 ULONG aulReservedForBIOS[2]; //Don't use them
2629 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2651 ULONG ulFirmwareRevision;
2652 ULONG ulDefaultEngineClock; //In 10Khz unit
2653 ULONG ulDefaultMemoryClock; //In 10Khz unit
2654 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2655 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2656 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2657 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2658 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2659 ULONG ulASICMaxEngineClock; //In 10Khz unit
2660 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2664 ULONG aulReservedForBIOS; //Don't use them
2665 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2666 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2688 ULONG ulFirmwareRevision;
2689 ULONG ulDefaultEngineClock; //In 10Khz unit
2690 ULONG ulDefaultMemoryClock; //In 10Khz unit
2691 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2692 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2693 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2694 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2695 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2696 ULONG ulASICMaxEngineClock; //In 10Khz unit
2697 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2703 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2704 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2727 ULONG ulFirmwareRevision;
2728 ULONG ulDefaultEngineClock; //In 10Khz unit
2729 ULONG ulDefaultMemoryClock; //In 10Khz unit
2730 ULONG ulReserved1;
2731 ULONG ulReserved2;
2732 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2733 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2734 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2735 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2736 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2742 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2743 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2777 ULONG ulFirmwareRevision;
2778 ULONG ulDefaultEngineClock; //In 10Khz unit
2779 ULONG ulDefaultMemoryClock; //In 10Khz unit
2780 ULONG ulSPLL_OutputFreq; //In 10Khz unit
2781 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
2782 …ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In…
2783 …ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In…
2784 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2785 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2786 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
2792 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2793 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2796 …ULONG ulReserved6; //Was usMinEngineClockPLL_Output and u…
2797 …ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and us…
2812 …ULONG ulReserved10[3]; // New added comparing to previous ver…
2833 ULONG ulBootUpEngineClock; //in 10kHz unit
2834 ULONG ulBootUpMemoryClock; //in 10kHz unit
2835 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2836 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2842 ULONG ulReserved[2];
2905 ULONG ulBootUpEngineClock; //in 10kHz unit
2906 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2907 ULONG ulBootUpUMAClock; //in 10kHz unit
2908 ULONG ulBootUpSidePortClock; //in 10kHz unit
2909 ULONG ulMinSidePortClock; //in 10kHz unit
2910 ULONG ulReserved2[6]; //must be 0x0 for the reserved
2911 ULONG ulSystemConfig; //see explanation below
2912 ULONG ulBootUpReqDisplayVector;
2913 ULONG ulOtherDisplayMisc;
2914 ULONG ulDDISlot1Config;
2915 ULONG ulDDISlot2Config;
2920 ULONG ulDockingPinCFGInfo;
2921 ULONG ulCPUCapInfo;
2926 ULONG ulHTLinkFreq; //in 10Khz
2933 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2934 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2941 ULONG ulReserved3[96]; //must be 0x0
3079 ULONG ulBootUpEngineClock; //in 10kHz unit
3080 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
3081 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
3082 ULONG ulBootUpUMAClock; //in 10kHz unit
3083 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3084 ULONG ulBootUpReqDisplayVector;
3085 ULONG ulOtherDisplayMisc;
3086 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3087 ULONG ulSystemConfig; //TBD
3088 ULONG ulCPUCapInfo; //TBD
3094 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3095 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3096 ULONG ulDDISlot2Config;
3097 ULONG ulDDISlot3Config;
3098 ULONG ulDDISlot4Config;
3099 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3103 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3104 …ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter f…
3105 …ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for …
3106 …ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for …
3107 ULONG ulReserved6[61]; //must be 0x0
3118 ULONG ulMCUcodeRomStartAddr;
3119 ULONG ulMCUcodeLength;
3120 ULONG ulSMCUcodeRomStartAddr;
3121 ULONG ulSMCUcodeLength;
3122 ULONG ulRLCVUcodeRomStartAddr;
3123 ULONG ulRLCVUcodeLength;
3124 ULONG ulTOCUcodeStartAddr;
3125 ULONG ulTOCUcodeLength;
3126 ULONG ulSMCPatchTableStartAddr;
3127 ULONG ulSmcPatchTableLength;
3128 ULONG ulSystemFlag;
3628 ULONG ulReserved0;
3666 ULONG ulReserved[2];
3962 ULONG ulStartAddrUsedByFirmware;
3976 ULONG ulStartAddrUsedByFirmware;
4350 ULONG ulACPIDeviceEnum; //Reserved for now
4450 ULONG ulStrengthControl; // DVOA strength control for CF
4715 …ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
4750 ULONG ulGpioMaskVal; // GPIO Mask value
4760 ULONG ulMaxVoltageLevel;
4777 ULONG ulReserved;
4838 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
4839 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
4848 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
4849 ULONG ulEfuseMin; // Min
4856 ULONG ulEvvDerateTdp;
4857 ULONG ulEvvDerateTdc;
4858 ULONG ulBoardCoreTemp;
4859 ULONG ulMaxVddc;
4860 ULONG ulMinVddc;
4861 ULONG ulLoadLineSlop;
4862 ULONG ulLeakageTemp;
4863 ULONG ulLeakageVoltage;
4872 ULONG ulLkgEncodeLn_MaxDivMin;
4873 ULONG ulLkgEncodeMax;
4874 ULONG ulLkgEncodeMin;
4875 ULONG ulEfuseLogisticAlpha;
4898 ULONG ulEvvLkgFactor;
4899 ULONG ulBoardCoreTemp;
4900 ULONG ulMaxVddc;
4901 ULONG ulMinVddc;
4902 ULONG ulLoadLineSlop;
4903 ULONG ulLeakageTemp;
4904 ULONG ulLeakageVoltage;
4913 ULONG ulLkgEncodeLn_MaxDivMin;
4914 ULONG ulLkgEncodeMax;
4915 ULONG ulLkgEncodeMin;
4916 ULONG ulEfuseLogisticAlpha;
4925 ULONG ulTdpDerateDPM0;
4926 ULONG ulTdpDerateDPM1;
4927 ULONG ulTdpDerateDPM2;
4928 ULONG ulTdpDerateDPM3;
4929 ULONG ulTdpDerateDPM4;
4930 ULONG ulTdpDerateDPM5;
4931 ULONG ulTdpDerateDPM6;
4932 ULONG ulTdpDerateDPM7;
4940 ULONG ulEvvLkgFactor;
4941 ULONG ulBoardCoreTemp;
4942 ULONG ulMaxVddc;
4943 ULONG ulMinVddc;
4944 ULONG ulLoadLineSlop;
4945 ULONG ulLeakageTemp;
4946 ULONG ulLeakageVoltage;
4955 ULONG ulLkgEncodeLn_MaxDivMin;
4956 ULONG ulLkgEncodeMax;
4957 ULONG ulLkgEncodeMin;
4958 ULONG ulEfuseLogisticAlpha;
4967 ULONG ulTdpDerateDPM0;
4968 ULONG ulTdpDerateDPM1;
4969 ULONG ulTdpDerateDPM2;
4970 ULONG ulTdpDerateDPM3;
4971 ULONG ulTdpDerateDPM4;
4972 ULONG ulTdpDerateDPM5;
4973 ULONG ulTdpDerateDPM6;
4974 ULONG ulTdpDerateDPM7;
4976 ULONG ulRoAlpha;
4977 ULONG ulRoBeta;
4978 ULONG ulRoGamma;
4979 ULONG ulRoEpsilon;
4980 ULONG ulATermRo;
4981 ULONG ulBTermRo;
4982 ULONG ulCTermRo;
4983 ULONG ulSclkMargin;
4984 ULONG ulFmaxPercent;
4985 ULONG ulCRPercent;
4986 ULONG ulSFmaxPercent;
4987 ULONG ulSCRPercent;
4988 ULONG ulSDCMargine;
5026 …ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same volta…
5027 …ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage …
5034 …ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage …
5039 …ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index,…
5051 ULONG ulBootUpEngineClock;
5052 ULONG ulDentistVCOFreq;
5053 ULONG ulBootUpUMAClock;
5055 ULONG ulBootUpReqDisplayVector;
5056 ULONG ulOtherDisplayMisc;
5057 ULONG ulGPUCapInfo;
5058 ULONG ulSB_MMIO_Base_Addr;
5062 ULONG ulMinEngineClock;
5063 ULONG ulSystemConfig;
5064 ULONG ulCPUCapInfo;
5072 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
5073 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
5074 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
5076 ULONG ulGMCRestoreResetTime;
5077 ULONG ulMinimumNClk;
5078 ULONG ulIdleNClk;
5079 ULONG ulDDR_DLL_PowerUpTime;
5080 ULONG ulDDR_PLL_PowerUpTime;
5089 ULONG SclkDpmBoostMargin;
5090 ULONG SclkDpmThrottleMargin;
5093 ULONG ulBoostEngineCLock;
5100 ULONG ulReserved3[15];
5214 ULONG ulPowerplayTable[128];
5221 ULONG uReserved:2;
5222 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5223 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5224 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5226 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5227 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5228 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5229 ULONG uReserved:2;
5236 ULONG TDP_config_all;
5249 ULONG ulBootUpEngineClock;
5250 ULONG ulDentistVCOFreq;
5251 ULONG ulBootUpUMAClock;
5253 ULONG ulBootUpReqDisplayVector;
5254 ULONG ulOtherDisplayMisc;
5255 ULONG ulGPUCapInfo;
5256 ULONG ulSB_MMIO_Base_Addr;
5260 ULONG ulMinEngineClock;
5261 ULONG ulSystemConfig;
5262 ULONG ulCPUCapInfo;
5272 ULONG ulReserved[19];
5274 ULONG ulGMCRestoreResetTime;
5275 ULONG ulMinimumNClk;
5276 ULONG ulIdleNClk;
5277 ULONG ulDDR_DLL_PowerUpTime;
5278 ULONG ulDDR_PLL_PowerUpTime;
5287 ULONG SclkDpmBoostMargin;
5288 ULONG SclkDpmThrottleMargin;
5291 ULONG ulBoostEngineCLock;
5306 ULONG ulLCDBitDepthControlVal;
5307 ULONG ulNbpStateMemclkFreq[4];
5310 ULONG ulNbpStateNClkFreq[4];
5481 ULONG ulBootUpEngineClock;
5482 ULONG ulDentistVCOFreq;
5483 ULONG ulBootUpUMAClock;
5485 ULONG ulBootUpReqDisplayVector;
5486 ULONG ulVBIOSMisc;
5487 ULONG ulGPUCapInfo;
5488 ULONG ulDISP_CLK2Freq;
5492 ULONG ulReserved2;
5493 ULONG ulSystemConfig;
5494 ULONG ulCPUCapInfo;
5495 ULONG ulReserved3;
5503 ULONG ulReserved[19];
5505 ULONG ulGMCRestoreResetTime;
5506 ULONG ulReserved4;
5507 ULONG ulIdleNClk;
5508 ULONG ulDDR_DLL_PowerUpTime;
5509 ULONG ulDDR_PLL_PowerUpTime;
5518 ULONG ulGPUReservedSysMemBaseAddrLo;
5519 ULONG ulGPUReservedSysMemBaseAddrHi;
5521 ULONG ulReserved5;
5533 ULONG ulLCDBitDepthControlVal;
5534 ULONG ulNbpStateMemclkFreq[4];
5535 ULONG ulPSPVersion;
5536 ULONG ulNbpStateNClkFreq[4];
5693 …ULONG ulPowerplayTable[128]; // Update comments here to link new …
5707 ULONG ulBootUpEngineClock;
5708 ULONG ulDentistVCOFreq;
5709 ULONG ulBootUpUMAClock;
5711 ULONG ulBootUpReqDisplayVector;
5712 ULONG ulVBIOSMisc;
5713 ULONG ulGPUCapInfo;
5714 ULONG ulDISP_CLK2Freq;
5718 ULONG ulReserved2;
5719 ULONG ulSystemConfig;
5720 ULONG ulCPUCapInfo;
5721 ULONG ulReserved3;
5732 ULONG ulReserved[2];
5735 ULONG ulGMCRestoreResetTime;
5736 ULONG ulReserved4;
5737 ULONG ulIdleNClk;
5738 ULONG ulDDR_DLL_PowerUpTime;
5739 ULONG ulDDR_PLL_PowerUpTime;
5748 ULONG ulGPUReservedSysMemBaseAddrLo;
5749 ULONG ulGPUReservedSysMemBaseAddrHi;
5750 ULONG ulReserved5[3];
5762 ULONG ulLCDBitDepthControlVal;
5763 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
5764 ULONG ulPSPVersion;
5765 ULONG ulNbpStateNClkFreq[4];
5787 ULONG ulBootUpEngineClock;
5788 ULONG ulDentistVCOFreq;
5789 ULONG ulBootUpUMAClock;
5790 ULONG ulReserved0[8];
5791 ULONG ulBootUpReqDisplayVector;
5792 ULONG ulVBIOSMisc;
5793 ULONG ulGPUCapInfo;
5794 ULONG ulReserved1;
5798 ULONG ulReserved2;
5799 ULONG ulSystemConfig;
5800 ULONG ulCPUCapInfo;
5801 ULONG ulReserved3;
5809 ULONG ulReserved[7];
5811 ULONG ulReserved6[10];
5812 ULONG ulGMCRestoreResetTime;
5813 ULONG ulReserved4;
5814 ULONG ulIdleNClk;
5815 ULONG ulDDR_DLL_PowerUpTime;
5816 ULONG ulDDR_PLL_PowerUpTime;
5825 ULONG ulGPUReservedSysMemBaseAddrLo;
5826 ULONG ulGPUReservedSysMemBaseAddrHi;
5827 ULONG ulReserved5[3];
5839 ULONG ulLCDBitDepthControlVal;
5840 ULONG ulNbpStateMemclkFreq[2];
5841 ULONG ulReserved7[2];
5842 ULONG ulPSPVersion;
5843 ULONG ulNbpStateNClkFreq[4];
5891 …ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in…
5916 …ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out …
5947 …ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out …
6431 ULONG ulTargetMemoryClock; //In 10Khz unit
6469 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
6608 ULONG ulEfuseValue;
6705 ULONG ulDllResetClkRange;
6711 ULONG ucMemBlkId:8;
6712 ULONG ulMemClockRange:24;
6714 ULONG ulMemClockRange:24;
6715 ULONG ucMemBlkId:8;
6722 ULONG ulAccess;
6728 ULONG aulMemData[1];
6750 #define VALUE_DWORD SIZEOF ULONG
6768 ULONG ulARB_SEQDataBuf[32];
6777 ULONG ulRegValue;
6783 ULONG ulMCUcodeVersion;
6784 ULONG ulMCUcodeRomStartAddr;
6785 ULONG ulMCUcodeLength;
6840 ULONG ulSignature;
6858 ULONG ulReserved;
6880 ULONG ulReserved;
6881 …ULONG ulFlags; // To enable/disable functionalities based on mem…
6882 …ULONG ulEngineClock; // Override of default engine clock for particular m…
6883 …ULONG ulMemoryClock; // Override of default memory clock for particular m…
6908 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory…
6944 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memor…
6980 …ULONG ulClkRange; // memory clock in 10kHz unit, when …
7017 …ULONG ulDllDisClock; // memory DLL will be disable when target memory cl…
7044 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
7066 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7108 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7140 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7172 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7203 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7227 ULONG ulChannelMapCfg1; // channel mapping for channel8~15
7228 ULONG ulBankMapCfg;
7229 ULONG ulReserved;
7263 …ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) …
7305 ULONG ulByte0BitRemapCh0;
7306 ULONG ulByte1BitRemapCh0;
7307 ULONG ulByte2BitRemapCh0;
7308 ULONG ulByte3BitRemapCh0;
7309 ULONG ulByte0BitRemapCh1;
7310 ULONG ulByte1BitRemapCh1;
7311 ULONG ulByte2BitRemapCh1;
7312 ULONG ulByte3BitRemapCh1;
7386 ULONG Ptr32_Bit;
7431 ULONG RsvdOffScrnMemSize;
7432 ULONG RsvdOffScrnMEmPtr;
7446 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
7474 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
7475 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
7490 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
7770 ULONG ulReserved;
7777 ULONG ulReserved;
7866 ULONG ulAnalogSetting[1];
7875 ULONG ulCondition;
7876 ULONG ulRegVal;
7880 ULONG ulCondition;
7882 ULONG ulRegVal;
8242 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8243 ULONG ulReserved1; // must set to 0
8244 ULONG ulReserved2; // must set to 0
8258 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8259 ULONG ulMiscInfo2;
8260 ULONG ulEngineClock;
8261 ULONG ulMemoryClock;
8273 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8274 ULONG ulMiscInfo2;
8275 ULONG ulEngineClock;
8276 ULONG ulMemoryClock;
8494 ULONG Signature;
8495 ULONG TableLength; //Length
8500 ULONG OemRevision;
8501 ULONG CreatorId;
8502 ULONG CreatorRevision;
8521 …ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of …
8522 …ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of t…
8523 ULONG Reserved[4]; //0x3C
8527 ULONG PCIBus; //0x4C
8528 ULONG PCIDevice; //0x50
8529 ULONG PCIFunction; //0x54
8534 ULONG Revision; //0x60
8535 ULONG ImageLength; //0x64