Lines Matching refs:DSI_READ
216 #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx))) macro
632 reg = DSI_READ(dsi, DSIM_STATUS_REG); in exynos_dsi_set_pll()
662 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); in exynos_dsi_enable_clock()
737 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); in exynos_dsi_disable_clock()
742 reg = DSI_READ(dsi, DSIM_PLLCTRL_REG); in exynos_dsi_disable_clock()
749 u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG); in exynos_dsi_enable_lane()
763 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); in exynos_dsi_init_link()
852 reg = DSI_READ(dsi, DSIM_STATUS_REG); in exynos_dsi_init_link()
858 reg = DSI_READ(dsi, DSIM_ESCMODE_REG); in exynos_dsi_init_link()
901 reg = DSI_READ(dsi, DSIM_MDRESOL_REG); in exynos_dsi_set_display_enable()
914 u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); in exynos_dsi_wait_for_hdr_fifo()
928 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); in exynos_dsi_set_cmd_lpm()
940 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); in exynos_dsi_force_bta()
1020 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); in exynos_dsi_read_from_fifo()
1059 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); in exynos_dsi_read_from_fifo()
1069 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); in exynos_dsi_read_from_fifo()
1088 reg = DSI_READ(dsi, DSIM_RXFIFO_REG); in exynos_dsi_read_from_fifo()
1244 status = DSI_READ(dsi, DSIM_INTSRC_REG); in exynos_dsi_irq()