Lines Matching refs:DSI_WRITE
214 #define DSI_WRITE(dsi, reg_idx, val) writel((val), \ macro
521 DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]); in exynos_dsi_reset()
624 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); in exynos_dsi_set_pll()
672 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); in exynos_dsi_enable_clock()
689 DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg); in exynos_dsi_set_phy_ctrl()
697 DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg); in exynos_dsi_set_phy_ctrl()
717 DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg); in exynos_dsi_set_phy_ctrl()
730 DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg); in exynos_dsi_set_phy_ctrl()
740 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); in exynos_dsi_disable_clock()
744 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); in exynos_dsi_disable_clock()
752 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); in exynos_dsi_enable_lane()
765 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); in exynos_dsi_init_link()
770 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); in exynos_dsi_init_link()
839 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); in exynos_dsi_init_link()
861 DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg); in exynos_dsi_init_link()
864 DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg); in exynos_dsi_init_link()
879 DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg); in exynos_dsi_set_display_mode()
883 DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg); in exynos_dsi_set_display_mode()
887 DSI_WRITE(dsi, DSIM_MSYNC_REG, reg); in exynos_dsi_set_display_mode()
892 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); in exynos_dsi_set_display_mode()
906 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); in exynos_dsi_set_display_enable()
935 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); in exynos_dsi_set_cmd_lpm()
942 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); in exynos_dsi_force_bta()
966 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); in exynos_dsi_send_to_fifo()
981 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); in exynos_dsi_send_to_fifo()
1004 DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg); in exynos_dsi_send_to_fifo()
1251 DSI_WRITE(dsi, DSIM_INTSRC_REG, status); in exynos_dsi_irq()
1257 DSI_WRITE(dsi, DSIM_INTMSK_REG, mask); in exynos_dsi_irq()