84 #define gsc_write(cfg, offset)	writel(cfg, ctx->regs + (offset))  macro
405 	gsc_write(cfg, GSC_SW_RESET);  in gsc_sw_reset()
424 	gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);  in gsc_sw_reset()
425 	gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);  in gsc_sw_reset()
426 	gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);  in gsc_sw_reset()
431 	gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);  in gsc_sw_reset()
432 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);  in gsc_sw_reset()
433 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);  in gsc_sw_reset()
480 	gsc_write(cfg, GSC_IRQ);  in gsc_handle_irq()
550 	gsc_write(cfg, GSC_IN_CON);  in gsc_src_set_fmt()
602 	gsc_write(cfg, GSC_IN_CON);  in gsc_src_set_transf()
629 	gsc_write(cfg, GSC_SRCIMG_OFFSET);  in gsc_src_set_size()
634 	gsc_write(cfg, GSC_CROPPED_SIZE);  in gsc_src_set_size()
646 	gsc_write(cfg, GSC_SRCIMG_SIZE);  in gsc_src_set_size()
664 	gsc_write(cfg, GSC_IN_CON);  in gsc_src_set_size()
697 	gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);  in gsc_src_set_buf_seq()
698 	gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);  in gsc_src_set_buf_seq()
699 	gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);  in gsc_src_set_buf_seq()
731 		gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],  in gsc_src_set_addr()
733 		gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],  in gsc_src_set_addr()
735 		gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],  in gsc_src_set_addr()
739 		gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));  in gsc_src_set_addr()
740 		gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));  in gsc_src_set_addr()
741 		gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));  in gsc_src_set_addr()
821 	gsc_write(cfg, GSC_OUT_CON);  in gsc_dst_set_fmt()
873 	gsc_write(cfg, GSC_IN_CON);  in gsc_dst_set_transf()
963 	gsc_write(cfg, GSC_PRE_SCALE_RATIO);  in gsc_set_prescaler()
990 				gsc_write(h_coef_8t[sc_ratio][i][j],  in gsc_set_h_coef()
1016 				gsc_write(v_coef_4t[sc_ratio][i][j],  in gsc_set_v_coef()
1029 	gsc_write(cfg, GSC_MAIN_H_RATIO);  in gsc_set_scaler()
1033 	gsc_write(cfg, GSC_MAIN_V_RATIO);  in gsc_set_scaler()
1055 	gsc_write(cfg, GSC_DSTIMG_OFFSET);  in gsc_dst_set_size()
1059 	gsc_write(cfg, GSC_SCALED_SIZE);  in gsc_dst_set_size()
1069 	gsc_write(cfg, GSC_DSTIMG_SIZE);  in gsc_dst_set_size()
1087 	gsc_write(cfg, GSC_OUT_CON);  in gsc_dst_set_size()
1140 	gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);  in gsc_dst_set_buf_seq()
1141 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);  in gsc_dst_set_buf_seq()
1142 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);  in gsc_dst_set_buf_seq()
1186 		gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],  in gsc_dst_set_addr()
1188 		gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],  in gsc_dst_set_addr()
1190 		gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],  in gsc_dst_set_addr()
1194 		gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));  in gsc_dst_set_addr()
1195 		gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));  in gsc_dst_set_addr()
1196 		gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));  in gsc_dst_set_addr()
1555 		gsc_write(cfg, GSC_ENABLE);  in gsc_ippdrv_start()
1561 		gsc_write(cfg, GSC_IN_CON);  in gsc_ippdrv_start()
1566 		gsc_write(cfg, GSC_OUT_CON);  in gsc_ippdrv_start()
1578 		gsc_write(cfg, GSC_IN_CON);  in gsc_ippdrv_start()
1583 		gsc_write(cfg, GSC_OUT_CON);  in gsc_ippdrv_start()
1590 		gsc_write(cfg, GSC_IN_CON);  in gsc_ippdrv_start()
1595 		gsc_write(cfg, GSC_OUT_CON);  in gsc_ippdrv_start()
1615 	gsc_write(cfg, GSC_ENABLE);  in gsc_ippdrv_start()
1645 	gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);  in gsc_ippdrv_stop()
1646 	gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);  in gsc_ippdrv_stop()
1647 	gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);  in gsc_ippdrv_stop()
1651 	gsc_write(cfg, GSC_ENABLE);  in gsc_ippdrv_stop()