258 	uint32_t DP;  member
1047 	intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in cdv_intel_dp_mode_set()
1048 	intel_dp->DP |= intel_dp->color_range;  in cdv_intel_dp_mode_set()
1051 		intel_dp->DP |= DP_SYNC_HS_HIGH;  in cdv_intel_dp_mode_set()
1053 		intel_dp->DP |= DP_SYNC_VS_HIGH;  in cdv_intel_dp_mode_set()
1055 	intel_dp->DP |= DP_LINK_TRAIN_OFF;  in cdv_intel_dp_mode_set()
1059 		intel_dp->DP |= DP_PORT_WIDTH_1;  in cdv_intel_dp_mode_set()
1062 		intel_dp->DP |= DP_PORT_WIDTH_2;  in cdv_intel_dp_mode_set()
1065 		intel_dp->DP |= DP_PORT_WIDTH_4;  in cdv_intel_dp_mode_set()
1069 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;  in cdv_intel_dp_mode_set()
1081 		intel_dp->DP |= DP_ENHANCED_FRAMING;  in cdv_intel_dp_mode_set()
1086 		intel_dp->DP |= DP_PIPEB_SELECT;  in cdv_intel_dp_mode_set()
1088 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1089 	DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);  in cdv_intel_dp_mode_set()
1507 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_start_link_train()  local
1509 	DP |= DP_PORT_EN;  in cdv_intel_dp_start_link_train()
1510 	DP &= ~DP_LINK_TRAIN_MASK;  in cdv_intel_dp_start_link_train()
1512 	reg = DP;	  in cdv_intel_dp_start_link_train()
1531 		reg = DP | DP_LINK_TRAIN_PAT_1;  in cdv_intel_dp_start_link_train()
1588 	intel_dp->DP = DP;  in cdv_intel_dp_start_link_train()
1599 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_complete_link_train()  local
1607 		reg = DP | DP_LINK_TRAIN_PAT_2;  in cdv_intel_dp_complete_link_train()
1669 	reg = DP | DP_LINK_TRAIN_OFF;  in cdv_intel_dp_complete_link_train()
1682 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_link_down()  local
1691 		DP &= ~DP_LINK_TRAIN_MASK;  in cdv_intel_dp_link_down()
1692 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1698 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()