79 	tmp = I915_READ(crt->adpa_reg);  in intel_crt_get_hw_state()
98 	tmp = I915_READ(crt->adpa_reg);  in intel_crt_get_flags()
288 		save_adpa = adpa = I915_READ(crt->adpa_reg);  in intel_ironlake_crt_detect_hotplug()
297 		if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,  in intel_ironlake_crt_detect_hotplug()
308 	adpa = I915_READ(crt->adpa_reg);  in intel_ironlake_crt_detect_hotplug()
327 	save_adpa = adpa = I915_READ(crt->adpa_reg);  in valleyview_crt_detect_hotplug()
334 	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,  in valleyview_crt_detect_hotplug()
341 	adpa = I915_READ(crt->adpa_reg);  in valleyview_crt_detect_hotplug()
390 		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &  in intel_crt_detect_hotplug()
396 	stat = I915_READ(PORT_HOTPLUG_STAT);  in intel_crt_detect_hotplug()
507 	save_bclrpat = I915_READ(bclrpat_reg);  in intel_crt_load_detect()
508 	save_vtotal = I915_READ(vtotal_reg);  in intel_crt_load_detect()
509 	vblank = I915_READ(vblank_reg);  in intel_crt_load_detect()
521 		uint32_t pipeconf = I915_READ(pipeconf_reg);  in intel_crt_load_detect()
542 			uint32_t vsync = I915_READ(vsync_reg);  in intel_crt_load_detect()
560 		while (I915_READ(pipe_dsl_reg) >= vactive)  in intel_crt_load_detect()
562 		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)  in intel_crt_load_detect()
575 		} while ((I915_READ(pipe_dsl_reg) == dsl));  in intel_crt_load_detect()
720 		adpa = I915_READ(crt->adpa_reg);  in intel_crt_reset()
876 		dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;  in intel_crt_init()