Lines Matching refs:I915_READ
592 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
675 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
683 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
697 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
703 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
716 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
948 wrpll = I915_READ(reg); in hsw_ddi_calc_wrpll_link()
985 cfgcr1_val = I915_READ(cfgcr1_reg); in skl_calc_wrpll_link()
986 cfgcr2_val = I915_READ(cfgcr2_reg); in skl_calc_wrpll_link()
1065 dpll_ctl1 = I915_READ(DPLL_CTRL1); in skl_ddi_clock_get()
1129 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; in hsw_ddi_clock_get()
1841 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_set_vc_payload_alloc()
1955 uint32_t val = I915_READ(reg); in intel_ddi_disable_transcoder_func()
1986 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_connector_get_hw_state()
2024 tmp = I915_READ(DDI_BUF_CTL(port)); in intel_ddi_get_hw_state()
2030 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); in intel_ddi_get_hw_state()
2048 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); in intel_ddi_get_hw_state()
2135 reg = I915_READ(DISPIO_CR_TX_BMU_CR0); in skl_ddi_set_iboost()
2186 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); in bxt_ddi_vswing_sequence()
2190 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); in bxt_ddi_vswing_sequence()
2196 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); in bxt_ddi_vswing_sequence()
2206 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); in bxt_ddi_vswing_sequence()
2211 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); in bxt_ddi_vswing_sequence()
2309 val = I915_READ(DPLL_CTRL1); in intel_ddi_pre_enable()
2321 val = I915_READ(DPLL_CTRL2); in intel_ddi_pre_enable()
2371 val = I915_READ(DDI_BUF_CTL(port)); in intel_ddi_post_disable()
2378 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_post_disable()
2394 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | in intel_ddi_post_disable()
2482 val = I915_READ(WRPLL_CTL(pll->id)); in hsw_ddi_wrpll_disable()
2492 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_disable()
2506 val = I915_READ(WRPLL_CTL(pll->id)); in hsw_ddi_wrpll_get_hw_state()
2521 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_get_hw_state()
2600 val = I915_READ(DPLL_CTRL1); in skl_ddi_pll_enable()
2616 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
2618 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) in skl_ddi_pll_enable()
2629 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); in skl_ddi_pll_disable()
2647 val = I915_READ(regs[pll->id].ctl); in skl_ddi_pll_get_hw_state()
2651 val = I915_READ(DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
2656 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); in skl_ddi_pll_get_hw_state()
2657 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); in skl_ddi_pll_get_hw_state()
2685 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in broxton_phy_init()
2690 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) in broxton_phy_init()
2698 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); in broxton_phy_init()
2712 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); in broxton_phy_init()
2717 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); in broxton_phy_init()
2723 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); in broxton_phy_init()
2729 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); in broxton_phy_init()
2734 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); in broxton_phy_init()
2754 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, in broxton_phy_init()
2758 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); in broxton_phy_init()
2765 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); in broxton_phy_init()
2770 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); in broxton_phy_init()
2787 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); in broxton_phy_uninit()
2815 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_enable()
2821 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); in bxt_ddi_pll_enable()
2826 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); in bxt_ddi_pll_enable()
2832 temp = I915_READ(BXT_PORT_PLL(port, 0)); in bxt_ddi_pll_enable()
2838 temp = I915_READ(BXT_PORT_PLL(port, 1)); in bxt_ddi_pll_enable()
2844 temp = I915_READ(BXT_PORT_PLL(port, 2)); in bxt_ddi_pll_enable()
2850 temp = I915_READ(BXT_PORT_PLL(port, 3)); in bxt_ddi_pll_enable()
2856 temp = I915_READ(BXT_PORT_PLL(port, 6)); in bxt_ddi_pll_enable()
2864 temp = I915_READ(BXT_PORT_PLL(port, 8)); in bxt_ddi_pll_enable()
2869 temp = I915_READ(BXT_PORT_PLL(port, 9)); in bxt_ddi_pll_enable()
2874 temp = I915_READ(BXT_PORT_PLL(port, 10)); in bxt_ddi_pll_enable()
2881 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); in bxt_ddi_pll_enable()
2889 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_enable()
2894 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & in bxt_ddi_pll_enable()
2902 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); in bxt_ddi_pll_enable()
2915 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_disable()
2931 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_get_hw_state()
2935 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); in bxt_ddi_pll_get_hw_state()
2938 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); in bxt_ddi_pll_get_hw_state()
2941 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); in bxt_ddi_pll_get_hw_state()
2944 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); in bxt_ddi_pll_get_hw_state()
2947 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); in bxt_ddi_pll_get_hw_state()
2950 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); in bxt_ddi_pll_get_hw_state()
2953 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); in bxt_ddi_pll_get_hw_state()
2958 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); in bxt_ddi_pll_get_hw_state()
2961 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); in bxt_ddi_pll_get_hw_state()
2964 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); in bxt_ddi_pll_get_hw_state()
2973 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); in bxt_ddi_pll_get_hw_state()
2974 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2977 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); in bxt_ddi_pll_get_hw_state()
3002 uint32_t val = I915_READ(LCPLL_CTL); in intel_ddi_pll_init()
3016 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) in intel_ddi_pll_init()
3047 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { in intel_ddi_prepare_link_retrain()
3048 val = I915_READ(DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
3055 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()
3092 val = I915_READ(FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_disable()
3096 val = I915_READ(FDI_RX_MISC(PIPE_A)); in intel_ddi_fdi_disable()
3101 val = I915_READ(FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_disable()
3105 val = I915_READ(FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_disable()
3119 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_get_config()
3171 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); in intel_ddi_get_config()
3293 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & in intel_ddi_init()