759 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)  in intel_ddi_get_crtc_new_encoder()  argument
761 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in intel_ddi_get_crtc_new_encoder()
769 	state = crtc_state->base.state;  in intel_ddi_get_crtc_new_encoder()
772 		if (connector_state->crtc != crtc_state->base.crtc)  in intel_ddi_get_crtc_new_encoder()
1268 		   struct intel_crtc_state *crtc_state,  in hsw_ddi_pll_select()  argument
1271 	int clock = crtc_state->port_clock;  in hsw_ddi_pll_select()
1284 		memset(&crtc_state->dpll_hw_state, 0,  in hsw_ddi_pll_select()
1285 		       sizeof(crtc_state->dpll_hw_state));  in hsw_ddi_pll_select()
1287 		crtc_state->dpll_hw_state.wrpll = val;  in hsw_ddi_pll_select()
1289 		pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in hsw_ddi_pll_select()
1296 		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);  in hsw_ddi_pll_select()
1297 	} else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {  in hsw_ddi_pll_select()
1298 		struct drm_atomic_state *state = crtc_state->base.state;  in hsw_ddi_pll_select()
1303 		    WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))  in hsw_ddi_pll_select()
1306 		crtc_state->shared_dpll = DPLL_ID_SPLL;  in hsw_ddi_pll_select()
1307 		spll->hw_state.spll = crtc_state->dpll_hw_state.spll;  in hsw_ddi_pll_select()
1562 		   struct intel_crtc_state *crtc_state,  in skl_ddi_pll_select()  argument
1567 	int clock = crtc_state->port_clock;  in skl_ddi_pll_select()
1595 		switch (crtc_state->port_clock / 2) {  in skl_ddi_pll_select()
1611 	memset(&crtc_state->dpll_hw_state, 0,  in skl_ddi_pll_select()
1612 	       sizeof(crtc_state->dpll_hw_state));  in skl_ddi_pll_select()
1614 	crtc_state->dpll_hw_state.ctrl1 = ctrl1;  in skl_ddi_pll_select()
1615 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;  in skl_ddi_pll_select()
1616 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;  in skl_ddi_pll_select()
1618 	pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in skl_ddi_pll_select()
1626 	crtc_state->ddi_pll_sel = pll->id + 1;  in skl_ddi_pll_select()
1655 		   struct intel_crtc_state *crtc_state,  in bxt_ddi_pll_select()  argument
1663 	int clock = crtc_state->port_clock;  in bxt_ddi_pll_select()
1673 		if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {  in bxt_ddi_pll_select()
1723 	memset(&crtc_state->dpll_hw_state, 0,  in bxt_ddi_pll_select()
1724 	       sizeof(crtc_state->dpll_hw_state));  in bxt_ddi_pll_select()
1737 	crtc_state->dpll_hw_state.ebb0 =  in bxt_ddi_pll_select()
1739 	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;  in bxt_ddi_pll_select()
1740 	crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);  in bxt_ddi_pll_select()
1741 	crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;  in bxt_ddi_pll_select()
1744 		crtc_state->dpll_hw_state.pll3 =  in bxt_ddi_pll_select()
1747 	crtc_state->dpll_hw_state.pll6 =  in bxt_ddi_pll_select()
1749 	crtc_state->dpll_hw_state.pll6 |=  in bxt_ddi_pll_select()
1752 	crtc_state->dpll_hw_state.pll8 = targ_cnt;  in bxt_ddi_pll_select()
1754 	crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;  in bxt_ddi_pll_select()
1756 	crtc_state->dpll_hw_state.pll10 =  in bxt_ddi_pll_select()
1760 	crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;  in bxt_ddi_pll_select()
1762 	crtc_state->dpll_hw_state.pcsdw12 =  in bxt_ddi_pll_select()
1765 	pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in bxt_ddi_pll_select()
1773 	crtc_state->ddi_pll_sel = pll->id;  in bxt_ddi_pll_select()
1786 			  struct intel_crtc_state *crtc_state)  in intel_ddi_pll_select()  argument
1790 		intel_ddi_get_crtc_new_encoder(crtc_state);  in intel_ddi_pll_select()
1793 		return skl_ddi_pll_select(intel_crtc, crtc_state,  in intel_ddi_pll_select()
1796 		return bxt_ddi_pll_select(intel_crtc, crtc_state,  in intel_ddi_pll_select()
1799 		return hsw_ddi_pll_select(intel_crtc, crtc_state,  in intel_ddi_pll_select()