Lines Matching refs:ddi_pll_sel
638 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); in hsw_fdi_link_train()
639 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); in hsw_fdi_link_train()
1063 dpll = pipe_config->ddi_pll_sel; in skl_ddi_clock_get()
1111 val = pipe_config->ddi_pll_sel; in hsw_ddi_clock_get()
1296 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); in hsw_ddi_pll_select()
1297 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { in hsw_ddi_pll_select()
1626 crtc_state->ddi_pll_sel = pll->id + 1; in skl_ddi_pll_select()
1773 crtc_state->ddi_pll_sel = pll->id; in bxt_ddi_pll_select()
2299 uint32_t dpll = crtc->config->ddi_pll_sel; in intel_ddi_pre_enable()
2331 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); in intel_ddi_pre_enable()
2332 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); in intel_ddi_pre_enable()