1284 		memset(&crtc_state->dpll_hw_state, 0,  in hsw_ddi_pll_select()
1285 		       sizeof(crtc_state->dpll_hw_state));  in hsw_ddi_pll_select()
1287 		crtc_state->dpll_hw_state.wrpll = val;  in hsw_ddi_pll_select()
1303 		    WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))  in hsw_ddi_pll_select()
1307 		spll->hw_state.spll = crtc_state->dpll_hw_state.spll;  in hsw_ddi_pll_select()
1611 	memset(&crtc_state->dpll_hw_state, 0,  in skl_ddi_pll_select()
1612 	       sizeof(crtc_state->dpll_hw_state));  in skl_ddi_pll_select()
1614 	crtc_state->dpll_hw_state.ctrl1 = ctrl1;  in skl_ddi_pll_select()
1615 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;  in skl_ddi_pll_select()
1616 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;  in skl_ddi_pll_select()
1723 	memset(&crtc_state->dpll_hw_state, 0,  in bxt_ddi_pll_select()
1724 	       sizeof(crtc_state->dpll_hw_state));  in bxt_ddi_pll_select()
1737 	crtc_state->dpll_hw_state.ebb0 =  in bxt_ddi_pll_select()
1739 	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;  in bxt_ddi_pll_select()
1740 	crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);  in bxt_ddi_pll_select()
1741 	crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;  in bxt_ddi_pll_select()
1744 		crtc_state->dpll_hw_state.pll3 =  in bxt_ddi_pll_select()
1747 	crtc_state->dpll_hw_state.pll6 =  in bxt_ddi_pll_select()
1749 	crtc_state->dpll_hw_state.pll6 |=  in bxt_ddi_pll_select()
1752 	crtc_state->dpll_hw_state.pll8 = targ_cnt;  in bxt_ddi_pll_select()
1754 	crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;  in bxt_ddi_pll_select()
1756 	crtc_state->dpll_hw_state.pll10 =  in bxt_ddi_pll_select()
1760 	crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;  in bxt_ddi_pll_select()
1762 	crtc_state->dpll_hw_state.pcsdw12 =  in bxt_ddi_pll_select()
2314 			val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);  in intel_ddi_pre_enable()