980 	uint32_t p0, p1, p2, dco_freq;  in skl_calc_wrpll_link()  local
992 		p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;  in skl_calc_wrpll_link()
994 		p1 = 1;  in skl_calc_wrpll_link()
1032 	return dco_freq / (p0 * p1 * p2 * 5);  in skl_calc_wrpll_link()
1170 	clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;  in bxt_calc_pll_link()
1363 				      unsigned int *p1 /* out */,  in skl_wrpll_get_multipliers()  argument
1372 			*p1 = 1;  in skl_wrpll_get_multipliers()
1376 			*p1 = half / 2;  in skl_wrpll_get_multipliers()
1380 			*p1 = half / 3;  in skl_wrpll_get_multipliers()
1384 			*p1 = half / 7;  in skl_wrpll_get_multipliers()
1389 		*p1 = 1;  in skl_wrpll_get_multipliers()
1393 		*p1 = 1;  in skl_wrpll_get_multipliers()
1397 		*p1 = 1;  in skl_wrpll_get_multipliers()
1401 		*p1 = 1;  in skl_wrpll_get_multipliers()
1405 		*p1 = 1;  in skl_wrpll_get_multipliers()
1423 				      uint32_t p0, uint32_t p1, uint32_t p2)  in skl_wrpll_params_populate()  argument
1472 	params->qdiv_ratio = p1;  in skl_wrpll_params_populate()
1475 	dco_freq = p0 * p1 * p2 * afe_clock;  in skl_wrpll_params_populate()
1510 	unsigned int p0, p1, p2;  in skl_ddi_calculate_wrpll()  local
1552 	p0 = p1 = p2 = 0;  in skl_ddi_calculate_wrpll()
1553 	skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);  in skl_ddi_calculate_wrpll()
1555 				  p0, p1, p2);  in skl_ddi_calculate_wrpll()
1634 	uint32_t p1;  member
1679 		clk_div.p1 = best_clock.p1;  in bxt_ddi_pll_select()
1699 		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;  in bxt_ddi_pll_select()
1738 		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);  in bxt_ddi_pll_select()