1109 	u32 val, pll;  in hsw_ddi_clock_get()  local
1129 		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;  in hsw_ddi_clock_get()
1130 		if (pll == SPLL_PLL_FREQ_810MHz)  in hsw_ddi_clock_get()
1132 		else if (pll == SPLL_PLL_FREQ_1350MHz)  in hsw_ddi_clock_get()
1134 		else if (pll == SPLL_PLL_FREQ_2700MHz)  in hsw_ddi_clock_get()
1154 	struct intel_shared_dpll *pll;  in bxt_calc_pll_link()  local
1162 	pll = &dev_priv->shared_dplls[dpll];  in bxt_calc_pll_link()
1163 	state = &pll->config.hw_state;  in bxt_calc_pll_link()
1274 		struct intel_shared_dpll *pll;  in hsw_ddi_pll_select()  local
1289 		pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in hsw_ddi_pll_select()
1290 		if (pll == NULL) {  in hsw_ddi_pll_select()
1296 		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);  in hsw_ddi_pll_select()
1565 	struct intel_shared_dpll *pll;  in skl_ddi_pll_select()  local
1618 	pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in skl_ddi_pll_select()
1619 	if (pll == NULL) {  in skl_ddi_pll_select()
1626 	crtc_state->ddi_pll_sel = pll->id + 1;  in skl_ddi_pll_select()
1658 	struct intel_shared_dpll *pll;  in bxt_ddi_pll_select()  local
1765 	pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in bxt_ddi_pll_select()
1766 	if (pll == NULL) {  in bxt_ddi_pll_select()
1773 	crtc_state->ddi_pll_sel = pll->id;  in bxt_ddi_pll_select()
2462 			       struct intel_shared_dpll *pll)  in hsw_ddi_wrpll_enable()  argument
2464 	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);  in hsw_ddi_wrpll_enable()
2465 	POSTING_READ(WRPLL_CTL(pll->id));  in hsw_ddi_wrpll_enable()
2470 				struct intel_shared_dpll *pll)  in hsw_ddi_spll_enable()  argument
2472 	I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);  in hsw_ddi_spll_enable()
2478 				  struct intel_shared_dpll *pll)  in hsw_ddi_wrpll_disable()  argument
2482 	val = I915_READ(WRPLL_CTL(pll->id));  in hsw_ddi_wrpll_disable()
2483 	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);  in hsw_ddi_wrpll_disable()
2484 	POSTING_READ(WRPLL_CTL(pll->id));  in hsw_ddi_wrpll_disable()
2488 				 struct intel_shared_dpll *pll)  in hsw_ddi_spll_disable()  argument
2498 				       struct intel_shared_dpll *pll,  in hsw_ddi_wrpll_get_hw_state()  argument
2506 	val = I915_READ(WRPLL_CTL(pll->id));  in hsw_ddi_wrpll_get_hw_state()
2513 				      struct intel_shared_dpll *pll,  in hsw_ddi_spll_get_hw_state()  argument
2591 			       struct intel_shared_dpll *pll)  in skl_ddi_pll_enable()  argument
2598 	dpll = pll->id + 1;  in skl_ddi_pll_enable()
2604 	val |= pll->config.hw_state.ctrl1 << (dpll * 6);  in skl_ddi_pll_enable()
2609 	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);  in skl_ddi_pll_enable()
2610 	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);  in skl_ddi_pll_enable()
2611 	POSTING_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_enable()
2612 	POSTING_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_enable()
2615 	I915_WRITE(regs[pll->id].ctl,  in skl_ddi_pll_enable()
2616 		   I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);  in skl_ddi_pll_enable()
2623 				struct intel_shared_dpll *pll)  in skl_ddi_pll_disable()  argument
2628 	I915_WRITE(regs[pll->id].ctl,  in skl_ddi_pll_disable()
2629 		   I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);  in skl_ddi_pll_disable()
2630 	POSTING_READ(regs[pll->id].ctl);  in skl_ddi_pll_disable()
2634 				     struct intel_shared_dpll *pll,  in skl_ddi_pll_get_hw_state()  argument
2645 	dpll = pll->id + 1;  in skl_ddi_pll_get_hw_state()
2647 	val = I915_READ(regs[pll->id].ctl);  in skl_ddi_pll_get_hw_state()
2656 		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_get_hw_state()
2657 		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_get_hw_state()
2810 				struct intel_shared_dpll *pll)  in bxt_ddi_pll_enable()  argument
2813 	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */  in bxt_ddi_pll_enable()
2828 	temp |= pll->config.hw_state.ebb0;  in bxt_ddi_pll_enable()
2834 	temp |= pll->config.hw_state.pll0;  in bxt_ddi_pll_enable()
2840 	temp |= pll->config.hw_state.pll1;  in bxt_ddi_pll_enable()
2846 	temp |= pll->config.hw_state.pll2;  in bxt_ddi_pll_enable()
2852 	temp |= pll->config.hw_state.pll3;  in bxt_ddi_pll_enable()
2860 	temp |= pll->config.hw_state.pll6;  in bxt_ddi_pll_enable()
2866 	temp |= pll->config.hw_state.pll8;  in bxt_ddi_pll_enable()
2871 	temp |= pll->config.hw_state.pll9;  in bxt_ddi_pll_enable()
2877 	temp |= pll->config.hw_state.pll10;  in bxt_ddi_pll_enable()
2885 	temp |= pll->config.hw_state.ebb4;  in bxt_ddi_pll_enable()
2905 	temp |= pll->config.hw_state.pcsdw12;  in bxt_ddi_pll_enable()
2910 					struct intel_shared_dpll *pll)  in bxt_ddi_pll_disable()  argument
2912 	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */  in bxt_ddi_pll_disable()
2922 					struct intel_shared_dpll *pll,  in bxt_ddi_pll_get_hw_state()  argument
2925 	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */  in bxt_ddi_pll_get_hw_state()